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    JOB SCHEDULING USING REINFORCEMENT LEARNING
    301.
    发明公开
    JOB SCHEDULING USING REINFORCEMENT LEARNING 审中-公开

    公开(公告)号：US20230154100A1

    公开(公告)日：2023-05-18

    申请号：US17529916

    申请日：2021-11-18

    Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

    Inventor： Thomas Daniel Perry ,  Steven Tovey ,  Mehdi Saeedi ,  Andrej Zdravkovic ,  Zhuo Chen

    IPC: G06T15/00 ,  G06F9/48

    CPC classification number: G06T15/005 ,  G06F9/4881 ,  G06N20/00

    Abstract: Systems, methods, and techniques utilize reinforcement learning to efficiently schedule a sequence of jobs for execution by one or more processing threads. A first sequence of execution jobs associated with rendering a target frame of a sequence of frames is received. One or more reward metrics related to rendering the target frame are selected. A modified sequence of execution jobs for rendering the target frame is generated, such as by reordering the first sequence of execution jobs. The modified sequence is evaluated with respect to the selected reward metric(s); and rendering the target frame is initiated based at least in part on the evaluating of the modified sequence with respect to the one or more selected reward metric(s).

    Combining Quantum States of Qubits on a Quantum Processor
    302.
    发明公开
    Combining Quantum States of Qubits on a Quantum Processor 审中-公开

    公开(公告)号：US20230153672A1

    公开(公告)日：2023-05-18

    申请号：US17840417

    申请日：2022-06-14

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Salonik Resch ,  Anthony Gutierrez ,  Mark H. Oskin

    IPC: G06N10/20

    CPC classification number: G06N10/20

    Abstract: An electronic device includes a quantum processor including a plurality of qubits. The quantum processor runs a plurality of instances of a quantum program using a separate set of qubits from among the qubits for each instance of the quantum program. The quantum processor then sets quantum states for ancilla qubits from among the qubits based on quantum states of respective groups of associated qubits from the separate sets of qubits. The quantum processor next provides an output of the instances of the quantum program based on the quantum states of the ancilla qubits.

    Prefetch disable of memory requests targeting data lacking locality
    305.
    发明授权
    Prefetch disable of memory requests targeting data lacking locality 有权

    公开(公告)号：US11645207B2

    公开(公告)日：2023-05-09

    申请号：US17132769

    申请日：2020-12-23

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Masab Ahmad ,  Derrick Allen Aguren

    IPC: G06F12/10 ,  G06F12/0862

    CPC classification number: G06F12/0862 ,  G06F2212/6028

    Abstract: A system and method for efficiently processing memory requests are described. A processing unit includes at least a processor core, a cache, and a non-cache storage buffer capable of storing data prevented from being stored in the cache. While processing a memory request targeting the non-cache storage buffer, the processor core inspects a flag stored in a tag of the memory request. The processor core prevents data prefetching into one or more of the non-cache storage buffer and the cache based on determining the flag specifies preventing data prefetching into one or more of the non-cache storage buffer and the cache using the target address of the memory request during processing of this instance of the memory request. While processing a prefetch hint instruction, the processor core determines from the tag whether to prevent prefetching.

    Method and apparatus for controlling cache line storage in cache memory
    308.
    发明授权
    Method and apparatus for controlling cache line storage in cache memory 有权

    公开(公告)号：US11636038B2

    公开(公告)日：2023-04-25

    申请号：US17575461

    申请日：2022-01-13

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： David A. Roberts

    IPC: G06F12/08 ,  G06F12/0846 ,  G06F12/0862 ,  G06F12/0815

    Abstract: A method and apparatus physically partitions clean and dirty cache lines into separate memory partitions, such as one or more banks, so that during low power operation, a cache memory controller reduces power consumption of the cache memory containing the clean only data. The cache memory controller controls refresh operation so that data refresh does not occur for clean data only banks or the refresh rate is reduced for clean data only banks. Partitions that store dirty data can also store clean data, however other partitions are designated for storing only clean data so that the partitions can have their refresh rate reduced or refresh stopped for periods of time. When multiple DRAM dies or packages are employed, the partition can occur on a die or package level as opposed to a bank level within a die.

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