公开(公告)号：US10362250B2

公开(公告)日：2019-07-23

申请号：US15985998

申请日：2018-05-22

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Guyader ,  Francois Roy

IPC: H04N5/353 ,  H04N5/374 ,  H04N5/378 ,  H01L27/146

Abstract: A global shutter image sensor of a back-illuminated type includes a semiconductor substrate and pixels. Each pixel includes a photosensitive area, a storage area, a readout area and areas for transferring charges between these different areas. The image sensor includes, for each pixel, a protector extending at least partly into the substrate from the back of the substrate to ensure that the storage area is protected against back illumination.

公开(公告)号：US10359652B2

公开(公告)日：2019-07-23

申请号：US15868642

申请日：2018-01-11

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Charles Baudot ,  Maurin Douix ,  Frederic Boeuf ,  Sébastien Cremer

IPC: G02F1/035 ,  G02F1/025 ,  G02F1/015

Abstract: An E/O phase modulator may include a waveguide having an insulating substrate, a single-crystal silicon strip and a polysilicon strip of a same thickness and doped with opposite conductivity types above the insulating substrate, and an insulating interface layer between the single-crystal silicon strip and polysilicon strip. Each of the single-crystal silicon strip and polysilicon strip may be laterally continued by a respective extension, and a respective electrical contact coupled to each extension.

公开(公告)号：US10354926B2

公开(公告)日：2019-07-16

申请号：US15723528

申请日：2017-10-03

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Benoît Froment ,  Stephan Niel ,  Arnaud Regnier ,  Abderrezak Marzaki

IPC: H01L21/8234 ,  H01L21/762 ,  H01L21/74 ,  H01L27/08 ,  H01L49/02 ,  H01C7/12 ,  H01L21/765 ,  H01L29/8605 ,  H01L23/522 ,  H01L29/06

Abstract: An integrated circuit includes a semiconductor substrate with an electrically isolated semiconductor well. An upper trench isolation extends from a front face of the semiconductor well to a depth located a distance from the bottom of the well. Two additional isolating zones are electrically insulated from the semiconductor well and extending inside the semiconductor well in a first direction and vertically from the front face to the bottom of the semiconductor well. At least one hemmed resistive region is bounded by the two additional isolating zones, the upper trench isolation and the bottom of the semiconductor well. Electrical contacts are electrically coupled to the hemmed resistive region.

公开(公告)号：US20190181180A1

公开(公告)日：2019-06-13

申请号：US15839011

申请日：2017-12-12

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H01L27/148 ,  H01L27/146

Abstract: An imaging cell includes a skimming gate transistor coupled between a photosensitive charge node and an intermediate node and a transfer gate transistor coupled between the intermediate node and a sense node. The skimming gate transistor includes a vertical gate electrode structure formed by a first capacitive deep trench isolation extending into a substrate and a second capacitive deep trench isolation extending into the substrate. A channel of the skimming gate transistor is positioned between the first and second capacitive deep trench isolations. Each capacitive deep trench isolation is formed by a trench that is lined with an insulating liner and filled with a conductive or semiconductive material.

公开(公告)号：US10319806B2

公开(公告)日：2019-06-11

申请号：US15220869

申请日：2016-07-27

Applicant: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Guillaume Rodriguez ,  Aomar Halimaoui ,  Laurent Ortiz

IPC: H01L27/108 ,  H01L49/02

Abstract: The electrode for a structure of Metal-Insulator-Metal type is formed by a stack successively comprising a gold layer, a barrier layer made from electrically conducting oxide and a platinum layer.The electrically conducting oxide is advantageously a noble metal oxide, and preferentially ruthenium oxide.The electrode is arranged on a substrate. The gold layer of the electrode is separated from the substrate by an adhesion layer made from titanium dioxide.The electrode is used to fabricate a capacitor of Metal-Insulator-Metal type.

公开(公告)号：US10304893B2

公开(公告)日：2019-05-28

申请号：US15592437

申请日：2017-05-11

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Daniel Benoit ,  Olivier Hinsinger ,  Emmanuel Gourvest

IPC: H01L27/146

Abstract: A back-side illuminated image sensor includes memory regions formed in a semiconductor wafer. Each memory region is located between two opaque walls which extend into the semiconductor wafer. An opaque screen is arranged at the rear surface of the memory region and in electrical contact with the opaque walls.

公开(公告)号：US10304775B2

公开(公告)日：2019-05-28

申请号：US15700960

申请日：2017-09-11

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Philippe Boivin ,  Delia Ristoiu

IPC: H01L23/535 ,  H01L23/48 ,  H01L21/768 ,  H01L23/485 ,  H01L27/12 ,  H01L23/532

Abstract: A connecting bar electrically connects separate circuit zones of an integrated circuit. The connecting bar is formed by a main portion that is a conductive strip extending above separate circuit zones to be interconnected. The conductive strip is separated from the integrated circuit by a dielectric except at the circuit zones to be interconnected. The connecting bar further includes secondary portions that are conductive pads passing through the dielectric in a vertical direction from the circuit zone to the conductive strip.

公开(公告)号：US20190146868A1

公开(公告)日：2019-05-16

申请号：US15810731

申请日：2017-11-13

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Om Ranjan ,  Riccardo Gemelli ,  Denis Dutey

IPC: G06F11/10 ,  G11C29/52

Abstract: Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.

公开(公告)号：US20190140072A1

公开(公告)日：2019-05-09

申请号：US15803959

申请日：2017-11-06

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Pascal Chevalier ,  Alexis Gauthier

IPC: H01L29/66 ,  H01L29/732 ,  H01L29/08

Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector connection region. A first epitaxial region forms a collector region doped with a first conductivity type on the collector connection region. The collector region includes a counter-doped region of a second conductivity type. A second epitaxial region forms a base region of a second conductivity type on the first epitaxial region. Deposited semiconductor material forms an emitter region of the first conductivity type on the second epitaxial region. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.

公开(公告)号：US20190131521A1

公开(公告)日：2019-05-02

申请号：US16168369

申请日：2018-10-23

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Pierre MORIN ,  Didier DUTARTRE

IPC: H01L45/00

Abstract: A memory cell includes a phase-change material. A via is connected to a transistor and an element for heating the phase-change material. A layer made of a material (which is one of electrically insulating or has an electric resistivity greater than 2.5·10−5 Ω·m and which is sufficiently thin to be crossable by an electric current due to a tunnel-type effect) is positioned between the via and the heating element. Interfaces between the layer and materials in contact with surfaces of said layer form a thermal barrier.