公开(公告)号：US20230102296A1

公开(公告)日：2023-03-30

申请号：US17490037

申请日：2021-09-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Michael W. Boyer ,  Ashish Gondimalla ,  Bradford M. Beckmann

IPC: G06F17/16

Abstract: A processing unit decomposes a matrix for partial processing at a processor-in-memory (PIM) device. The processing unit receives a matrix to be used as an operand in an arithmetic operation (e.g., a matrix multiplication operation). In response, the processing unit decomposes the matrix into two component matrices: a sparse component matrix and a dense component matrix. The processing unit itself performs the arithmetic operation with the dense component matrix, but sends the sparse component matrix to the PIM device for execution of the arithmetic operation. The processing unit thereby offloads at least some of the processing overhead to the PIM device, improving overall efficiency of the processing system.

公开(公告)号：US20230102183A1

公开(公告)日：2023-03-30

申请号：US17489182

申请日：2021-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Deepak Vasant Kulkarni ,  Rahul Agarwal ,  Rajasekaran Swaminathan ,  Chintan Buch

IPC: H01L23/495 ,  H01L23/14

Abstract: Apparatuses, systems and methods for efficiently generating a package substrate. A semiconductor fabrication process (or process) fabricates each of a first glass package substrate and a second glass package substrate with a redistribution layer on a single side of a respective glass wafer. The process flips the second glass package substrate upside down and connects the glass wafers of the first and second glass package substrates together using a wafer bonding technique. In some implementations, the process uses copper-based wafer bonding. The resulting bonding between the two glass wafers contains no air gap, no underfill, and no solder bumps. Afterward, the side of the first glass package substrate opposite the glass wafer is connected to at least one integrated circuit. Additionally, the side of the second glass package substrate opposite the glass wafer is connected to a component on the motherboard through pads on the motherboard.

公开(公告)号：US20230101640A1

公开(公告)日：2023-03-30

申请号：US17483698

申请日：2021-09-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Mihir Shaileshbhai Doctor ,  Alexander J. Branover ,  Benjamin Tsien ,  Indrani Paul ,  Christopher T. Weaver ,  Thomas J. Gibney ,  Stephen V. Kosonocky ,  John P. Petry

IPC: G06F1/3287 ,  G06F1/3234 ,  G06F1/3296

Abstract: Devices and methods for linear addressing are provided. A device is provided which comprises a plurality of components having assigned registers used to store data to execute a program and a power management controller, in communication with the components. The power management controller is configured to send one of a request to remove power to the components and a request to reduce power to the components when it is determined that the components are idle, execute a first process of one of removing power and reducing power to the components and entering a reduced power state when an acknowledgement of the request is received and execute a second process of restoring power to the components when one or more of the components are indicated to be active.

公开(公告)号：US20230101038A1

公开(公告)日：2023-03-30

申请号：US17489741

申请日：2021-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Patrick J. Shyvers

IPC: G06F12/0891 ,  G06F12/02 ,  G06F3/06 ,  G06F1/08

Abstract: A method and processing device for accessing data is provided. The processing device comprises a cache and a processor. The cache comprises a first data section having a first cache hit latency and a second data section having a second cache hit latency that is different from the first cache hit latency of the first data section. The processor is configured to request access to data in memory, the data corresponding to a memory address which includes an identifier that identifies the first data section of the cache. The processor is also configured to load the requested data, determined to be located in the first data section of the cache, according to the first cache hit latency of the first data section of the cache.

公开(公告)号：US20230100491A1

公开(公告)日：2023-03-30

申请号：US17487929

申请日：2021-09-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： PENG LI ,  CHANGWEI LIANG

IPC: H01R12/88

Abstract: A socket actuation mechanism for package insertion and package-socket alignment, including: a socket frame comprising a plurality of first hinge portions; a carrier frame comprising: a center portion comprising one or more package interlocks; and a tab extending from a first end of the carrier frame, the tab comprising a second hinge portion couplable with the plurality of first hinge portions to form a hinge coupling the carrier frame to the socket frame.

公开(公告)号：US20230100230A1

公开(公告)日：2023-03-30

申请号：US17488206

申请日：2021-09-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul J. Moyer

IPC: G06F12/0897 ,  G06F12/0864 ,  G06F12/123 ,  G06F12/02

Abstract: Systems and methods are disclosed for maintaining insertion policies of a lower-level cache. Techniques are described for selecting, based on metadata of an evicted data block received from an upper-level cache, an insertion policy out of the insertion policies. Then, determining, based on the selected insertion policy, whether to insert the data block into the lower-level cache. If it is determined to insert, the data block is inserted into the lower-level cache according to the selected insertion policy. Techniques for dynamically updating the insertion policies of the lower-level cache are also disclosed.

公开(公告)号：US20230098181A1

公开(公告)日：2023-03-30

申请号：US17485966

申请日：2021-09-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： CHRISTOPHER M. JAGGERS

IPC: H05K7/20 ,  G06F1/18

Abstract: A computing device chassis for a common cooling solution for die packages comprising: a chassis base comprising: an internal cavity; a cooling element housed in the internal cavity; and one or more thermal interfaces to the cooling element.

公开(公告)号：US20230096002A1

公开(公告)日：2023-03-30

申请号：US17890520

申请日：2022-08-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Ranjith Kumar SAJJA ,  Sreekanth GODEY ,  Anirudh R. ACHARYA

IPC: G06F1/08 ,  G06F9/50 ,  G06F11/34 ,  G06F1/12

Abstract: Systems and methods related to controlling clock signals for clocking shader engines modules (SEs) and non-shader-engine modules (nSEs) of a graphics processing unit (GPU) are provided. One or more dividers receive a clock signal CLK and output a clock signal CLKA to the SEs and output a clock signal CLKB to the nSEs. The frequencies of CLKA and CLKB are independently selected based on sets of performance counter data monitored at the SEs and nSEs, respectively. The clock signal frequency for either the SEs or the nSEs is reduced when the corresponding sets of performance counter data indicates a comparatively lower processing workload for the SEs or for the nSEs.

公开(公告)号：US20230094384A1

公开(公告)日：2023-03-30

申请号：US17487103

申请日：2021-09-28

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： DMITRI TIKHOSTOUP ,  DANIEL WAIHIM WONG ,  WILLIAM HERZ

IPC: G06F9/50

Abstract: A dynamic allocator for providing platform resource candidates is disclosed. In an implementation, a platform resource allocator receives a request from a workload initiator such as, an application, for a platform resource recommendation. The platform resource allocator analyzes performance capabilities and utilization metrics of a plurality of platform resources for each of a plurality of resource. The plurality of platform resources includes one or more graphics processor units (GPUs) and one or more accelerated processing units (APUs). The platform resource allocator dynamically provides the platform resource recommendation to the workload initiator to select one or more of the plurality of platform resources to execute a workload based on the performance capabilities and utilization metrics.

公开(公告)号：US20230092184A1

公开(公告)日：2023-03-23

申请号：US17483672

申请日：2021-09-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Richard T. Schultz

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/02

Abstract: A system and method for creating chip layout are described. In various implementations, a standard cell uses unidirectional tracks for power connections and signal routing. A single track of the metal one layer that uses a minimum width of the metal one layer is placed within a pitch of a single metal gate. The single track of the metal one layer provides a power supply reference voltage level or ground reference voltage level. This placement of the single track provides a metal one power post contacted gate pitch (CPP) of 1 CPP. To further reduce voltage droop, a standard cell uses dual height and half the width of a single height cell along with placing power posts with 1 CPP. The placement of the multiple power rails of the dual height cell allows alignment of the power rails with power rails of other standard cells.