公开(公告)号：US20130264677A1

公开(公告)日：2013-10-10

申请号：US13859418

申请日：2013-04-09

Applicant: STMICROELECTRONICS SA

Inventor： Philippe GALY ,  Jean JIMENEZ

IPC: H01L27/02 ,  H01L21/77

CPC classification number: H01L27/0207 ,  H01L21/76264 ,  H01L21/77 ,  H01L27/088 ,  H01L27/1211 ,  H01L29/0692 ,  H01L29/435 ,  H01L29/78 ,  H01L29/7824 ,  H01L29/7825

Abstract: At least three electrically conducting blocks are disposed within an isolating region; and at least two of them are mutually separated and capacitively coupled by a part of the isolating region. At least two of them, being semiconductor, have opposite types of conductivity or identical types of conductivity, but with different concentrations of dopants, and these are in mutual contact by one of their sides. The mutual arrangement of these blocks within the isolating region, their type of conductivity and their concentration of dopants form at least one electronic module. Some of the blocks define input and output blocks.

Abstract translation: 至少三个导电块设置在隔离区内; 并且它们中的至少两个被隔离区域的一部分相互分离和电容耦合。 它们中的至少两个是半导体，具有相反的导电性或相同类型的导电性，但是具有不同浓度的掺杂剂，并且这些掺杂物的两侧之间相互接触。 这些块在隔离区域内的相互排列，它们的导电类型及其掺杂剂的浓度形成至少一个电子模块。 一些块定义输入和输出块。

公开(公告)号：US20130223138A1

公开(公告)日：2013-08-29

申请号：US13836690

申请日：2013-03-15

Applicant: STMicroelectronics SA

Inventor： Philippe Candelier ,  Laurent Dedieu ,  Noureddine Larhriq

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C7/24 ,  G11C8/20 ,  G11C11/41 ,  G11C16/22

Abstract: A secure memory includes a bistable memory cell having a programmed start-up state, and means for flipping the state of the cell in response to a flip signal. The memory may include a clock for generating the flip signal with a period, for example, smaller than the acquisition time of an emission microscope.

Abstract translation: 安全存储器包括具有编程的启动状态的双稳态存储单元，以及用于响应于翻转信号翻转单元的状态的装置。 存储器可以包括用于以例如小于发射显微镜的获取时间的周期产生翻转信号的时钟。

公开(公告)号：US20130214326A1

公开(公告)日：2013-08-22

申请号：US13768730

申请日：2013-02-15

Applicant: STMICROELECTRONICS SA

Inventor： Philippe Galy ,  Nicolas Guitard ,  Thomas Benoist

IPC: H01L29/74

CPC classification number: H01L29/7424 ,  H01L27/0262 ,  H01L29/87

Abstract: A device includes, within a layer of silicon on insulator, a central semiconductor zone including a central region having a first type of conductivity, two intermediate regions having a second type of conductivity opposite to that of the first one, respectively disposed on either side of and in contact with the central region in order to form two PN junctions, two semiconductor end zones respectively disposed on either side of the central zone, each end zone comprising two end regions of opposite types of conductivity, in contact with the adjacent intermediate region, the two end regions of each end zone being mutually connected electrically in order to form the two terminals of the device.

Abstract translation: 一种器件包括在绝缘体上的硅层内的包括具有第一类型导电性的中心区域的中心半导体区域，具有与第一类型导电性相反的第二类型导电率的第二类型的中间区域分别设置在 并且与中心区域接触以形成两个PN结，两个半导体端部区域分别设置在中心区域的任一侧上，每个端部区域包括与相邻中间区域接触的相反导电类型的两个端部区域， 每个端部区域的两个端部区域相互电连接以形成装置的两个端子。

公开(公告)号：US20130075870A1

公开(公告)日：2013-03-28

申请号：US13622573

申请日：2012-09-19

Applicant: STMicoelectronics (Crolles 2) SAS ,  STMicroelectronics SA,

Inventor： Didier Dutartre ,  Michel Marty ,  Sebastien Jouan

IPC: H01L21/3105 ,  H01L23/58

CPC classification number: H01L21/76898 ,  H01L21/76251

Abstract: A device and corresponding fabrication method includes a vertical stack having an intermediate layer between a lower region and an upper region. The intermediate layer is extended by a protection layer. The vertical stack has a free lateral face on which the lower region, the upper region and the protection layer are exposed.

Abstract translation: 一种器件和相应的制造方法包括在下部区域和上部区域之间具有中间层的垂直堆叠。 中间层由保护层延伸。 垂直堆叠具有自由侧面，下部区域，上部区域和保护层暴露在该侧面上。

公开(公告)号：US20040266112A1

公开(公告)日：2004-12-30

申请号：US10852057

申请日：2004-05-24

Applicant: STMicroelectronics SA

Inventor： Thomas Skotnicki ,  Emmanuel Josse

IPC: H01L021/332 ,  H01L021/336 ,  H01L021/4763 ,  H01L021/8238

CPC classification number: H01L29/66666 ,  H01L29/165 ,  H01L29/7827

Abstract: The vertical insulated gate transistor includes, on a semiconductor substrate, a vertical pillar incorporating one of the source and drain regions at the top, a gate dielectric layer situated on the flanks of the pillar and on the top surface of the substrate, and a semiconductor gate resting on the gate dielectric layer. The other of the source and drain regions is in the bottom part of the pillar PIL and the insulated gate includes an isolated external portion 15 resting on the flanks of the pillar and an isolated internal portion 14 situated inside the pillar between the source and drain regions. The isolated internal portion is separated laterally from the isolated external portion by two connecting semiconductor regions PL1, PL2 extending between the source and drain regions, and forming two very fine pillars.

公开(公告)号：US20040257467A1

公开(公告)日：2004-12-23

申请号：US10782651

申请日：2004-02-19

Applicant: STMICROELECTRONICS SA

Inventor： Marina Nicolas

IPC: H04N011/20

CPC classification number: H04N7/012 ,  H04N5/144 ,  H04N7/0137

Abstract: The invention provides for a process and a device for de-interlacing a video signal, wherein at output (S) is produced a signal (Sde) of video images de-interlaced by interpolating the pixels missing from the interlaced video signal presented at input (E), the interpolation on the output signal (Sde) being composed selectively (10) from a spatial interpolation (6), based on a transition detection and from a temporal interpolation (8) with a decision being made on the variable degree of presence of spatial interpolation and/or of temporal interpolation in the output signal (Sde), the decision being made as a function of a motion detection in the relevant area of the image, wherein the decision is made additionally as a function of a detection of the detail (2) in a relevant area of the image.

Abstract translation: 本发明提供了一种用于对视频信号进行去隔行扫描的过程和设备，其中在输出（S）处产生视频图像的信号（Sde），该视频图像通过内插来自在输入处呈现的隔行视频信号丢失的像素而被去隔行扫描 E），基于转移检测和来自对可变存在度的决定的时间插值（8），从空间插值（6）选择性地（10）地输出输出信号（Sde）上的内插 在所述输出信号（Sde）中进行空间插值和/或时间内插的判定，所述判定作为所述图像的相关区域中的运动检测的函数，其中，所述判定作为附加检测的函数 细节（2）在图像的相关区域。

公开(公告)号：US20040246997A1

公开(公告)日：2004-12-09

申请号：US10824932

申请日：2004-04-15

Applicant: STMicroelectronics SA

Inventor： Ludovic Ruat ,  Paul Kinowski ,  Alexander Czajor

IPC: H04L005/16

CPC classification number: G06F13/385 ,  H04L7/044 ,  H04L7/046

Abstract: A asynchronous frame receiver includes an input for receiving asynchronous frames. The asynchronous frames include standard characters, and a header that has a data bit length greater than a data bit length of the standard characters. A break character detection unit detects the break character. A standard character processing unit for detecting the standard characters is activated by the break character detection unit based upon the break character being detected.

Abstract translation: 异步帧接收器包括用于接收异步帧的输入。 异步帧包括标准字符和数据位长度大于标准字符的数据位长度的报头。 中断字符检测单元检测断点字符。 用于检测标准字符的标准字符处理单元由断点字符检测单元基于检测到的断点字符来激活。

公开(公告)号：US20040132260A1

公开(公告)日：2004-07-08

申请号：US10714440

申请日：2003-11-14

Applicant: STMicroelectronics SA

Inventor： Damien Lenoble

IPC: H01L021/336

CPC classification number: H01L29/6659 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/665

Abstract: A process for fabricating an integrated circuit includes forming a gate on a crystalline silicon substrate, and amorphizing a region of the substrate to obtain an amorphous silicon region. Dopant is implanted in a subregion lying substantially within the amorphous silicon region of the substrate to form drain and source extensions. A source and drain are then formed at a low temperature.

Abstract translation: 一种用于制造集成电路的工艺包括在晶体硅衬底上形成栅极，并使基片的区域非晶化以获得非晶硅区域。 掺杂剂被植入在基本上位于衬底的非晶硅区域内的子区域中以形成漏极和源极延伸。 然后在低温下形成源极和漏极。

公开(公告)号：US20040113665A1

公开(公告)日：2004-06-17

申请号：US10688208

申请日：2003-10-17

Applicant: STMicroelectronics SA

Inventor： Loic Joet ,  Sebastien Dedieu ,  Eric Andre ,  Daniel Saias

IPC: H03L007/06

CPC classification number: H03L7/087 ,  H03L7/0891 ,  H03L7/183 ,  H03L7/199 ,  H03L2207/18

Abstract: A method for generating a signal with a frequency equal to a product of a reference frequency and a real number includes providing an output signal from an oscillator, and performing a first integer division of a frequency of the output signal by a first integer divider to obtain a first intermediate signal. A first measurement signal representative of a time difference between the first intermediate signal and a reference signal having the reference frequency is determined. The method further includes generating a first comparison signal derived from the first measurement signal, and generating a second comparison signal dependent on a period of the reference signal, on integer and decimal parts of the real number and on the first integer divider. The first and second comparison signals are compared to obtain an error signal representative of a time difference between a period of a current output signal and the period of the reference signal. The first integer division is deactivated to deliver an error signal to the input of the oscillator, with the output signal from the oscillator forming the desired signal with a frequency equal to the product of the reference frequency and the real number.

Abstract translation: 用于产生频率等于参考频率和实数的乘积的信号的方法包括提供来自振荡器的输出信号，以及通过第一整数分频器对输出信号的频率进行第一整数除法以获得 第一中间信号。 确定代表第一中间信号和具有参考频率的参考信号之间的时间差的第一测量信号。 该方法还包括生成从第一测量信号导出的第一比较信号，以及根据参考信号的周期，在实数的整数和小数部分以及第一整数分频器上产生第二比较信号。 比较第一和第二比较信号以获得表示当前输出信号的周期与参考信号周期之间的时间差的误差信号。 第一个整数除法被去激活以向振荡器的输入端发送一个误差信号，来自振荡器的输出信号形成期望的信号，其频率等于参考频率和实数的乘积。

公开(公告)号：US20040062108A1

公开(公告)日：2004-04-01

申请号：US10383153

申请日：2003-03-06

Applicant: STMicroelectronics SA

Inventor： Cyrille Dray ,  Phillipe Gendrier ,  Richard Fournel

IPC: G11C007/00

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11558 ,  H01L29/66825 ,  H01L29/7883

Abstract: The semiconductor memory device includes a non-volatile programmable and electrically erasable memory cell with a single layer of gate material and a floating gate transistor and a control gate, within an active semiconducting area formed in a region of the substrate and delimited by an isolation region. The layer of gate material in which the floating gate is made extends integrally above the active area without overlapping part of the isolation region, and the transistor is electrically isolated from the control gate by PN junctions that will be inverse polarized.

Abstract translation: 半导体存储器件包括具有单层栅极材料的非易失性可编程和电可擦除存储单元，以及浮置栅极晶体管和控制栅极，该有源半导体区域形成在衬底的区域中并由隔离区限定 。 其中制造浮栅的栅极材料层在有源区域上整体地延伸而不重叠隔离区的一部分，并且晶体管通过将被反极化的PN结与控制栅极电隔离。