Optical display screen device
    331.
    发明申请
    Optical display screen device 审中-公开
    光学显示屏设备

    公开(公告)号:US20060268106A1

    公开(公告)日:2006-11-30

    申请号:US11434285

    申请日:2006-05-15

    CPC classification number: G02B5/0242

    Abstract: A display screen is provided having both a diffusion layer and an absorption layer. The screen may be formed by coextrusion and may be suitable for use in rear projection applications.

    Abstract translation: 提供具有扩散层和吸收层的显示屏。 屏幕可以通过共挤出形成,并且可以适用于后投影应用。

    Marginless status determination circuit
    332.
    发明申请
    Marginless status determination circuit 失效
    无边缘状态确定电路

    公开(公告)号:US20060208745A1

    公开(公告)日:2006-09-21

    申请号:US11238957

    申请日:2005-09-30

    CPC classification number: G01R31/31727

    Abstract: By including a unit for storing data to be determined, a unit for delaying the data, a unit for storing the output of the delay unit, and a unit for comparing the storage contents of the data before the delay with the storage contents of the data after the delay, and outputting a marginless status detection signal when they are different, the presence/absence of a margin is monitored regardless of ambient conditions by using an output marginless status detection signal as a switch control signal for a clock switch circuit, thereby operating electronic equipment without changing a frequency of a clock signal up to the critical condition.

    Abstract translation: 通过包括用于存储要确定的数据的单元,用于延迟数据的单元,用于存储延迟单元的输出的单元,以及用于将延迟之前的数据的存储内容与数据的存储内容进行比较的单元 在延迟之后,并且当它们不同时输出无余位状态检测信号,通过使用输出无余位状态检测信号作为时钟切换电路的开关控制信号,无论环境条件如何,都监视是否存在余量,从而操作 电子设备,而不改变时钟信号的频率,直到临界状态。

    Production equipment monitoring device

    公开(公告)号:US07102622B2

    公开(公告)日:2006-09-05

    申请号:US10266612

    申请日:2002-10-09

    CPC classification number: G05B19/042

    Abstract: A production equipment monitoring device comprises a display panel providing a touch switch function, a touch switch display controller displaying on the display panel a touch switch corresponding to a general segmentary operating process, an operating status display controller distinguishably displaying thereon an operating status of the touch switch corresponding to the general segmentary operating process presently executed, a detail process information memory memorizing a name of a detail operating process and an address of the programmable logic controller to be referred thereto when judging an actual status of the detail operating process, and a detail information display controller displaying thereon, when the touch switch is pressed, the name of the detail operating process included in the general segmentary operating process corresponding to the pressed touch switch, and the actual status of the detail operating process obtained by the address of the programmable logic controller.

    Exposure analyzing system, method for analyzing exposure condition, and method for manufacturing semiconductor device
    334.
    发明申请
    Exposure analyzing system, method for analyzing exposure condition, and method for manufacturing semiconductor device 审中-公开
    曝光分析系统,曝光条件分析方法以及制造半导体器件的方法

    公开(公告)号:US20060172207A1

    公开(公告)日:2006-08-03

    申请号:US11044266

    申请日:2005-01-28

    CPC classification number: G03F7/70641 G03F7/70625

    Abstract: An exposure analyzing system includes a microscope measuring CDs in resist patterns, each of the resist patterns being formed by specific defocus and dose conditions, an exposure condition calculator calculating functions of the specific defocus and dose conditions, each of the functions giving one of the CDs, an image arranger arranging images of the resist patterns in a matrix having a first coordinate axis arranging the defocus conditions and a second coordinate axis arranging the dose conditions, and a graphic controller displaying the images and the functions in a coordinate plane implemented by the first and second coordinate axes.

    Abstract translation: 曝光分析系统包括显微镜测量抗蚀剂图案的CD,每个抗蚀剂图案通过特定的散焦和剂量条件形成,曝光条件计算器计算特定散焦和剂量条件的功能,每个功能给出一个CD 图像排列器,其将具有布置散焦条件的第一坐标轴的阵列中的抗蚀剂图案的图像和排列剂量条件的第二坐标轴布置;以及图形控制器,其在由第一 和第二坐标轴。

    Recording method and recording device

    公开(公告)号:US20060140088A1

    公开(公告)日:2006-06-29

    申请号:US11320347

    申请日:2005-12-28

    Applicant: Kenji Yoshida

    Inventor: Kenji Yoshida

    Abstract: A recording device and a method therefor for recording data on a given recording medium having a maximum number of recording units available for recording and a maximum number of sub-recording units within each recording unit determined by a format thereof. In the method and device, a restriction is applied so as not to enable an additional recording on the recording medium at the time when a number of the recording units recorded on the recording medium has reached the maximum number of recording units and recording of up to a first sub-recording unit within the last recording unit has been performed. Thus, it becomes possible to prevent occurrence of a situation, which is difficult for a user to understand, e.g. the situation where the remaining capacity for recording suddenly disappears owing to e.g. change in recording mode when recording on the recording medium is performed with a recording device.

    Decoder and decoding method for decoding low-density parity-check codes with parity check matrix
    337.
    发明申请
    Decoder and decoding method for decoding low-density parity-check codes with parity check matrix 有权
    用奇偶校验矩阵解码低密度奇偶校验码的解码和解码方法

    公开(公告)号:US20060005105A1

    公开(公告)日:2006-01-05

    申请号:US11168329

    申请日:2005-06-29

    Applicant: Kenji Yoshida

    Inventor: Kenji Yoshida

    CPC classification number: H03M13/1168 H03M13/1137 H03M13/114 H03M13/116

    Abstract: In an LDPC-code decoder, bit-processing units are provided, respectively, for the 1st to Mth rows of the parity-check matrix that is formed of (r×s) permuted matrices having respective arrays of (m×m) Each of bit-processing units sequentially updates bit information corresponding to column positions included in the respective rows of the parity-check matrix, a bit at each of the column positions being set to “1”. parity-processing units update parity information corresponding to row positions in columns of each column block of the parity-check matrix, whenever the bit-processing units have finished bit update computation for m column positions in each column block, a bit at each row position being set to “1”. The bit-processing units starts next bit update computation after the parity-processing units finish parity update computation for m columns of the first column block of the parity-check matrix.

    Abstract translation: 在LDPC码解码器中,对于由(rxs)形成的奇偶校验矩阵的第1个到第0个行分别提供比特处理单元 )排列的矩阵,每个位处理单元顺序地更新与奇偶校验矩阵的各行中包括的列位置相对应的位信息,每个列位置的位被设置为“1” 。 奇偶校验处理单元每当位处理单元对每个列块中的m列位置进行比特更新计算时,更新与奇偶校验矩阵的每个列块的列中的行位置相对应的奇偶校验信息,每行位置的位 被设置为“1”。 在奇偶校验处理单元完成奇偶校验矩阵的第一列块的m列的奇偶校验更新计算之后,位处理单元开始下一位更新计算。

    Multilayer optical display device
    338.
    发明申请
    Multilayer optical display device 审中-公开
    多层光学显示装置

    公开(公告)号:US20060003239A1

    公开(公告)日:2006-01-05

    申请号:US10882989

    申请日:2004-06-30

    CPC classification number: G02B5/0242

    Abstract: A multilayer optical device which comprises one or more radiation scattering layers, radiation absorption layers, tint layers, interfacial layers, adhesive layers, protective layers, matte, non-reflective, anti-glare, antistatic or embossed surface layers, focusing layers and supporting layers is described. Interfacial layers, adhesive layers, protective layers, tint layers, matte, non-reflective, anti-glare, antistatic or embossed surface layers, focusing layers and supporting layers may be optional in some embodiments of the invention. The device is used to display an image which is projected either in the transmission or reflection mode.

    Abstract translation: 一种多层光学器件,包括一个或多个辐射散射层,辐射吸收层,着色层,界面层,粘合剂层,保护层,无光泽,非反射性,防眩光,抗静电或压花表面层,聚焦层和支撑层 被描述。 在本发明的一些实施例中,界面层,粘合剂层,保护层,着色层,无光泽,非反射性,防眩光,抗静电或压花表面层,聚焦层和支撑层可以是任选的。 该设备用于显示投影在传输或反射模式下的图像。

    Novel gene having reverse transcriptas motif
    339.
    发明申请
    Novel gene having reverse transcriptas motif 审中-公开
    具有逆转录本基序的新基因

    公开(公告)号:US20050272092A1

    公开(公告)日:2005-12-08

    申请号:US11199124

    申请日:2005-08-09

    CPC classification number: C12N9/1276 C12Y207/07049

    Abstract: The present invention aims to provide a novel gene having a reverse transcriptase motif. The invention isolates a novel gene having a reverse transcriptase motif, and gives its complete base sequence determined. The invention also provides a protein encoded by the gene, and an antibody against the protein. The use of them is useful in developing a method for detecting telomerase activity, a method for detecting a cancer cell, a telomerase activity inhibitor, and a method for screening a telomerase activity inhibitor.

    Abstract translation: 本发明旨在提供具有逆转录酶基序的新基因。 本发明分离具有逆转录酶基序的新基因,并确定其完整的碱基序列。 本发明还提供了由该基因编码的蛋白质和针对该蛋白质的抗体。 其使用可用于开发端粒酶活性检测方法,癌细胞检测方法,端粒酶活性抑制剂及筛选端粒酶活性抑制剂的方法。

    Logic circuit for fast carry/borrow
    340.
    发明授权
    Logic circuit for fast carry/borrow 失效
    用于快速携带/借位的逻辑电路

    公开(公告)号:US06781412B2

    公开(公告)日:2004-08-24

    申请号:US10073132

    申请日:2002-02-13

    CPC classification number: G06F7/5055 G06F7/503

    Abstract: Each binary carry logic circuit 20 of half adder circuits other than that for the least significant digit comprises a transfer gate 212 turned on when an input bit A2 is active and receiving a carry-in bit *C2 at its data input, and a transistor 23, turned on when the input bit A2 is inactive, connected between a power supply potential VDD and the data output of the transfer gate 212 a signal on which is a carry-out bit *C3. Transfer gates 212 to 214 of binary carry logic circuits other than that for the least significant digit are connected in chain, and are simultaneously on/off controlled by input bits A2 to A4, letting the carry-in bit *C2 from the least significant digit propagate through the transfer gate chain at a high speed.

    Abstract translation: 除了最低有效位之外的半加法器电路的每个二进制进位逻辑电路20包括当输入位A2有效并在其数据输入端接收进位位* C2的传输门212导通,并且晶体管23 ,当输入位A2不活动时,在电源电位VDD和传输门212的数据输出之间连接作为进位位* C3的信号。 二进制逻辑电路以外的二进制进位逻辑电路的转移门212至214串联连接,同时由输入位A2至A4进行开/关控制,使来自最低有效位的进位位* C2 通过传输门链高速传播。

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