公开(公告)号：US20140241539A1

公开(公告)日：2014-08-28

申请号：US14271128

申请日：2014-05-06

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Anupam JAIN ,  Rakhel Kumar PARIDA

IPC: G10K11/00

CPC classification number: G10K11/002 ,  G10L21/0208 ,  G10L21/0232 ,  H04L5/0008 ,  H04L25/03159 ,  H04L27/2649 ,  H04L2025/03414

Abstract: A system for noise removal is coupled to a signal unit that provides a digital signal. The noise removal system includes a transformation module to transform the digital signal into an f-digital signal, a threshold filter to generate a noiseless signal from the f-digital signal based on a threshold profile, and a signal synthesizer to provide a gain to the noiseless signal and to transform the noiseless signal into an output signal.

Abstract translation: 用于噪声去除的系统耦合到提供数字信号的信号单元。 噪声去除系统包括：将数字信号变换为f数字信号的变换模块，基于阈值分布的f数字信号产生无噪声信号的阈值滤波器;以及信号合成器，用于向 并将无噪声信号变换为输出信号。

公开(公告)号：US20140233321A1

公开(公告)日：2014-08-21

申请号：US14266468

申请日：2014-04-30

Applicant: STMicroelectronics International N.V.

Inventor： Vikas RANA

IPC: G11C16/14 ,  G11C16/26

CPC classification number: G11C16/14 ,  G11C8/08 ,  G11C16/06 ,  G11C16/26

Abstract: A word-line driver includes first, second and third transistors. The first transistor includes a gate terminal driven by a first group selection signal, a first conduction terminal driven by a second sub-group selection signal and a second conduction terminal coupled to the word-line. The second transistor includes a gate terminal driven by a second group selection signal, a second conduction terminal driven by the second sub-group selection signal, and a first conduction terminal coupled to the word-line. The third transistor includes a gate terminal driven by a third the group selection signal, a first conduction terminal driven by a first sub-group selection signal, and a second conduction terminal coupled to the word-line.

Abstract translation: 字线驱动器包括第一，第二和第三晶体管。 第一晶体管包括由第一组选择信号驱动的栅极端子，由第二子组选择信号驱动的第一导通端子和耦合到字线的第二导通端子。 第二晶体管包括由第二组选择信号驱动的栅极端子，由第二子组选择信号驱动的第二导通端子和耦合到字线的第一导电端子。 第三晶体管包括由组选择信号的第三组驱动的栅极端子，由第一子组选择信号驱动的第一导通端子和耦合到字线的第二导通端子。

公开(公告)号：US08780615B2

公开(公告)日：2014-07-15

申请号：US13422906

申请日：2012-03-16

Applicant: Naveen Batra ,  Rajiv Kumar ,  Saurabh Agrawal

Inventor： Naveen Batra ,  Rajiv Kumar ,  Saurabh Agrawal

IPC: G11C11/00

CPC classification number: G11C7/12 ,  G11C8/08 ,  G11C11/413

Abstract: In a memory device, a bitline write voltage is applied to a first bitline. A wordline voltage is applied to a first wordline for writing data to a first memory cell connected to the first wordline and the first bitline. The first bitline and the second bitline are electrically connected for charge sharing between the first bitline and the second bitline. A predetermined time after electrically connecting the first bitline and the second bitline, the first and the second bitline are electrically disconnected and the bitline write voltage is applied to the second bitline. The wordline voltage is applied to a second wordline for writing data to a second memory cell connected to the second wordline and the second bitline.

Abstract translation: 在存储器件中，位线写入电压被施加到第一位线。 将字线电压施加到第一字线，以将数据写入连接到第一字线和第一位线的第一存储器单元。 第一位线和第二位线被电连接用于第一位线和第二位线之间的电荷共享。 在电连接第一位线和第二位线之后的预定时间，第一和第二位线被电断开，并且位线写入电压被施加到第二位线。 字线电压被施加到第二字线，用于将数据写入连接到第二字线和第二位线的第二存储器单元。

公开(公告)号：US08775857B2

公开(公告)日：2014-07-08

申请号：US13152013

申请日：2011-06-02

Applicant: Shray Khullar ,  Swapnil Bahl

Inventor： Shray Khullar ,  Swapnil Bahl

IPC: G06F1/08 ,  G06F1/06 ,  G06F11/22 ,  G01R31/3185

CPC classification number: G06F1/06 ,  G01R31/318552 ,  G01R31/318555 ,  G06F11/22

Abstract: A controller includes a clock control unit configured to provide a first output to test circuitry and a bypass unit configured to provide a second output to a further controller. The controller is configured to cause the bypass unit to output the second output and to optionally cause the clock control unit to output the first output.

Abstract translation: 控制器包括时钟控制单元，其被配置为向测试电路提供第一输出和配置成向另一个控制器提供第二输出的旁路单元。 控制器被配置为使旁路单元输出第二输出，并且可选地使时钟控制单元输出第一输出。

公开(公告)号：US08738679B2

公开(公告)日：2014-05-27

申请号：US12565596

申请日：2009-09-23

Applicant: Rakhel Kumar Parida ,  Ankur Bal ,  Anupam Jain

Inventor： Rakhel Kumar Parida ,  Ankur Bal ,  Anupam Jain

IPC: G06F17/17 ,  H03H17/06

CPC classification number: H03H17/0664 ,  H03H17/0282 ,  H03H17/0657 ,  H03H17/0671

Abstract: An offset free sinc interpolating filter includes differentiators operating at a first sampling frequency, integrators operating at a second sampling frequency and one or more coefficient multipliers. The coefficient multipliers multiply a received value with a constant coefficient value to generate an output value. The differentiators, integrators and coefficient multipliers can be operatively coupled to each other, either directly or through other components such as adders and delay elements, or by a combination of the two. In operation, an input signal is provided to the sinc interpolating filter at the first sampling frequency. The input signal is processed by the differentiators, integrators and coefficient multipliers to generate an output signal at the second sampling frequency. Once the output signal is generated, the integrators are reset before the next input cycle begins.

Abstract translation: 无偏移的正弦内插滤波器包括以第一采样频率工作的微分器，以第二采样频率工作的积分器和一个或多个系数乘法器。 系数乘法器将接收到的值与常数系数值相乘以产生输出值。 微分器，积分器和系数乘法器可以直接地或通过其他部件（例如加法器和延迟元件）或两者的组合来可操作地耦合。 在操作中，输入信号以第一采样频率提供给正弦内插滤波器。 输入信号由微分器，积分器和系数乘法器处理，以产生第二采样频率的输出信号。 产生输出信号后，积分器在下一个输入周期开始之前被复位。

公开(公告)号：US08731072B2

公开(公告)日：2014-05-20

申请号：US12857381

申请日：2010-08-16

Applicant: Ravi Ananthapur Bacche

Inventor： Ravi Ananthapur Bacche

IPC: H04N13/00

CPC classification number: H04N19/139 ,  H04N9/78 ,  H04N19/117 ,  H04N19/182 ,  H04N19/597

Abstract: An adaptive temporal motion filter for a video decoder system operates in an infinite impulse response (IIR), a max or a bypass mode. The adaptive temporal motion filter includes an adaptive time constant control module and a filter gain module. A gain factor of the filter gain module is varied by the adaptive time constant control module for every pixel in a current composite video signal. The adaptive time constant control module selects a variable gain for the filter gain module based on the motion magnitude, motion polarity and chroma luma status of the pixel.

Abstract translation: 用于视频解码器系统的自适应时间运动滤波器以无限脉冲响应（IIR），最大或旁路模式操作。 自适应时间运动滤波器包括自适应时间常数控制模块和滤波器增益模块。 滤波增益模块的增益因子由当前复合视频信号中每个像素的自适应时间常数控制模块改变。 自适应时间常数控制模块基于像素的运动幅度，运动极性和色度状态来选择滤波器增益模块的可变增益。

公开(公告)号：US20140112081A1

公开(公告)日：2014-04-24

申请号：US13655160

申请日：2012-10-18

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Anuj Grover ,  Gangaikondan Subramani Visweswaran

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G11C5/146 ,  G11C11/4074 ,  G11C11/41 ,  G11C11/412 ,  G11C11/417 ,  G11C16/30

Abstract: A memory cell includes a true data node, a true pullup transistor, a complement data node and a complement pullup transistor. A true switching circuit selectively supplies a first or second supply voltage to a source of the true pullup transistor. A true bias switching circuit selectively supplies a third or fourth supply voltage to a body of the true pullup transistor. When writing a logic high data value to the true data storage node, a control circuit causes the true switching circuit to supply the second supply voltage and the true bias switching circuit to supply the third supply voltage. The second supply voltage is higher than the first supply voltage, and the fourth supply voltage is higher than the third supply voltage. A similar operation is performed with respect to the complement pullup transistor when writing a logic high data value to the complement data storage node.

Abstract translation: 存储单元包括真实数据节点，真实上拉晶体管，补码数据节点和补码上拉晶体管。 真正的开关电路选择性地将第一或第二电源电压提供给真正的上拉晶体管的源极。 真正的偏置开关电路选择性地将第三或第四电源电压提供给真正的上拉晶体管的主体。 当将逻辑高数据值写入真实数据存储节点时，控制电路使真正的开关电路提供第二电源电压和真偏压开关电路来提供第三电源电压。 第二电源电压高于第一电源电压，第四电源电压高于第三电源电压。 当向补码数据存储节点写入逻辑高数据值时，相对于补码上拉晶体管执行类似的操作。

公开(公告)号：US08704952B2

公开(公告)日：2014-04-22

申请号：US13250581

申请日：2011-09-30

Applicant: Ravindranath Ramalingaiah Munnan

Inventor： Ravindranath Ramalingaiah Munnan

IPC: H04N9/66

CPC classification number: H04N9/455

Abstract: A video decoder that separates and analyzes analog video signals includes a hue and saturation separator and a video signal determiner. The hue and saturation separator demodulates from a component video signal chroma signal, which includes a hue signal and a saturation signal. The video signal determiner determines at least one video signal characteristic of the component video signal dependent on the hue and saturation signal. The video signal determiner may include a mode determiner that determines the encoding standard of the video signal, and a color burst determiner that determines a location of a color burst signal with the video signal. The mode determiner may include a signal lock detector, a sequence matcher, and an encoding mode selector. The color burst determiner may include an absolute value determiner and a burst position determiner.

Abstract translation: 分离和分析模拟视频信号的视频解码器包括色相和饱和分离器以及视频信号确定器。 色相和饱和度分离器从包括色相信号和饱和信号的分量视频信号色度信号解调。 视频信号确定器根据色相和饱和度信号确定分量视频信号的至少一个视频信号特性。 视频信号确定器可以包括确定视频信号的编码标准的模式确定器以及用视频信号确定色同步信号的位置的色同步确定器。 模式确定器可以包括信号锁定检测器，序列匹配器和编码模式选择器。 色同步确定器可以包括绝对值确定器和突发位置确定器。

公开(公告)号：US08681534B2

公开(公告)日：2014-03-25

申请号：US13339580

申请日：2011-12-29

Applicant: Nishu Kohli ,  Hiten Advani

Inventor： Nishu Kohli ,  Hiten Advani

IPC: G11C11/00 ,  G11C8/00

CPC classification number: G11C11/412

Abstract: A memory cell is formed by storage latch having a true node and a complement node. The cell includes a write port operable in response to a write signal on a write word line to write data from write bit lines into the latch, and a separate read port operable in response to a read signal on a read word line to read data from the latch to a read bit line. The circuitry of the memory cell is configured to address voltage bounce at the complement node during reading of the memory (where the voltage bounce arises from a simultaneous write to another memory cell in a same row).

Abstract translation: 存储单元由具有真实节点和补码节点的存储锁存器形成。 该单元包括可响应写入字线上的写入信号而工作的写入端口，以便将数据从写入位线写入锁存器，以及独立的读取端口，可响应读取字线上的读取信号读取数据， 锁存到读位线。 存储器单元的电路被配置为在读取存储器期间（其中电压反弹从同时写入到同一行中的另一个存储器单元）来解决补码节点处的电压反弹。

公开(公告)号：US20140009430A1

公开(公告)日：2014-01-09

申请号：US13544713

申请日：2012-07-09

Applicant: Francesco Italia ,  Giuseppe Noviello ,  Chee Yu Ng ,  Benedetto Vigna

Inventor： Francesco Italia ,  Giuseppe Noviello ,  Chee Yu Ng ,  Benedetto Vigna

IPC: G06F3/044

CPC classification number: G06F3/044 ,  G06F3/0416

Abstract: A touch sensitive display includes a capacitive touch sensor configured to output capacitance values. A motion sensor makes a motion detection and generates a motion signal including a motion value indicative of sensed motion detection. A touch detection circuit is coupled to receive the capacitance values and motion values. The touch detection circuit processes the capacitance values to make a hovering detection and a touching detection with respect to the display. The touch detection circuit further generates an output signal including the motion value correlated in time with each of the hovering detection and touching detection. The output signal may be processed as a user interface control signal. The output signal may also be processed to determine an impulsive strength of the touching detection as a function of an elapsed time between hover and touch and the measured motion values.

Abstract translation: 触敏显示器包括被配置为输出电容值的电容式触摸传感器。 运动传感器进行运动检测并产生运动信号，该运动信号包括指示检测到的运动检测的运动值。 耦合触摸检测电路以接收电容值和运动值。 触摸检测电路处理电容值以对显示进行悬停检测和触摸检测。 触摸检测电路进一步生成包括与悬停检测和触摸检测中的每一个相关的运动值的输出信号。 可以将输出信号作为用户界面控制信号进行处理。 还可以处理输出信号以确定触摸检测的脉冲强度作为在悬停和触摸之间经过的时间以及所测量的运动值的函数。