公开(公告)号：US20190155159A1

公开(公告)日：2019-05-23

申请号：US16094119

申请日：2017-04-07

Applicant: ASM IP HOLDING B.V. ,  IMEC VZW

Inventor： Werner Knaepen ,  Jan Willem Maes ,  Maarten Stokhof ,  Roel Gronheid ,  Hari Pathangi Sriraman

IPC: G03F7/16

Abstract: A method of forming a directed self-assembled (DSA) layer on a substrate by: providing a substrate; applying a layer comprising a self-assembly material on the substrate; and annealing of the self-assembly material of the layer to form a directed self-assembled layer by providing a controlled temperature and gas environment around the substrate. The controlled gas environment comprises molecules comprising an oxygen element with a partial pressure between 10-2000 Pa.

公开(公告)号：US20190153593A1

公开(公告)日：2019-05-23

申请号：US16258187

申请日：2019-01-25

Applicant: ASM IP Holding B.V.

Inventor： Chiyu Zhu ,  Kiran Shrestha ,  Suvi Haukka

IPC: C23C16/38 ,  C23C16/455

Abstract: A method for depositing a metal film onto a substrate is disclosed. In particular, the method comprises pulsing a metal halide precursor onto the substrate and pulsing a decaborane precursor onto the substrate. A reaction between the metal halide precursor and the decaborane precursor forms a metal film, specifically a metal boride.

公开(公告)号：US20190148398A1

公开(公告)日：2019-05-16

申请号：US16039867

申请日：2018-07-19

Applicant: ASM IP Holding B.V.

Inventor： Young Hoon Kim ,  Jong Wan Choi ,  Jeong Jun Woo ,  Tae Hee Yoo

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/822 ,  H01L21/311

Abstract: Provided is a substrate processing method capable of preventing over-etching of a part of a stair-case structure due to an etching solution, when a barrier layer is selectively formed on a VNAND device having the stair-case structure. The substrate processing method includes: alternately stacking a first insulating layer and a second insulating layer; forming a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface to the lower surface by etching the first insulating layer and the second insulating layer that are stacked; densifying the stepped structure; forming a barrier layer on the densified second insulating layer; and performing isotropic etching on at least a part of a sacrificial word line structure including the second insulating layer and the barrier layer. During etching the barrier layer at the isotropic etching step, the second insulating layer is not etched or etched a little to an ignorable degree.

公开(公告)号：US10290523B2

公开(公告)日：2019-05-14

申请号：US15461950

申请日：2017-03-17

Applicant: ASM IP Holding B.V.

Inventor： Toshihisa Nozawa

IPC: H01L21/67 ,  H01L21/677 ,  H01L21/68 ,  G05B19/418

Abstract: A wafer processing apparatus includes a controller connected to a first robot and a second robot. The controller controls the first robot so that the wafer is placed on a first load lock stage in such a way that the center of the wafer is shifted from the center of the first load lock stage by a first position shift amount and another wafer is placed on a second load lock stage in such a way that the center of the wafer is shifted from the center of the second load lock stage by a second position shift amount. The controller controls the second robot so that the second robot simultaneously conveys two wafers between the first and second load lock stages, and a first processing stage and a second processing stage.

公开(公告)号：US20190140067A1

公开(公告)日：2019-05-09

申请号：US16240392

申请日：2019-01-04

Applicant: ASM IP Holding B.V.

Inventor： Chiyu Zhu ,  Timo Asikainen ,  Robert Brennan Milligan

IPC: H01L29/49 ,  C23C16/32 ,  H01L21/28 ,  C23C16/455 ,  H01L21/02 ,  C23C16/04 ,  H01L21/3205 ,  H01L21/285

Abstract: Methods of forming thin-film structures including one or more NbMC layers, and structures and devices including the one or more NbMC layers are disclosed. The NbMC layers enable tuning of various structure and device properties, including resistivity, current leakage, and work function.

公开(公告)号：US20190139808A1

公开(公告)日：2019-05-09

申请号：US16031613

申请日：2018-07-10

Applicant: ASM IP HOLDING B.V.

Inventor： Carl Louis White ,  Kyle Fondurulia ,  John Kevin Shugrue ,  David Marquardt

IPC: H01L21/687 ,  C23C16/458 ,  C23C16/455 ,  C23C16/44

Abstract: The present disclosure relates to a semiconductor processing apparatus having a reaction chamber which can include a baseplate having an opening; a moveable substrate support configured to support a substrate; a movement element configured to move a substrate held on the substrate support towards the opening of the baseplate; a plurality of gas inlets positioned above and configured to direct gas downwardly towards the substrate support; and a sealing element configured to form a seal between the baseplate and the substrate support, the seal positioned at a greater radial distance from a center of the substrate support than an outer edge of the substrate support. In some embodiments, the sealing element can also include a plurality of apertures extend through the sealing element, the apertures configured to provide a flow path between a position below the sealing element to a position above the sealing element. Some embodiments include two or more stacked sealing elements.

公开(公告)号：US10283353B2

公开(公告)日：2019-05-07

申请号：US15472750

申请日：2017-03-29

Applicant: ASM IP Holding B.V. ,  National University Corporation Nagoya University

Inventor： Akiko Kobayashi ,  Masaru Zaitsu ,  Nobuyoshi Kobayashi ,  Masaru Hori

IPC: H01L21/3105 ,  H01L21/02 ,  H01L21/033

Abstract: A method of reforming an insulating film deposited on a substrate having a recess pattern constituted by a bottom and sidewalls, includes: providing the film deposited on the substrate having the recess pattern in an evacuatable reaction chamber, wherein a property of a portion of the film deposited on the sidewalls is inferior to that of a portion of the film deposited on a top surface of the substrate; adjusting a pressure of an atmosphere of the reaction chamber to 10 Pa or less, which atmosphere is constituted by H2 and/or He without a precursor and without a reactant; and applying RF power to the atmosphere of the pressure-adjusted reaction chamber to generate a plasma to which the film is exposed, thereby reforming the portion of the film deposited on the sidewalls to improve the property of the sidewall portion of the film.

公开(公告)号：US20190115206A1

公开(公告)日：2019-04-18

申请号：US15949990

申请日：2018-04-10

Applicant: ASM IP HOLDING B.V.

Inventor： Young Hoon Kim ,  Yong Gyu Han ,  Dae Youn Kim ,  Tae Hee Yoo ,  Wan Gyu Lim ,  Jin Geun Yu

IPC: H01L21/02 ,  H01L21/033 ,  H01L21/311 ,  C23C16/50 ,  C23C16/455 ,  C23C16/34

Abstract: Provided is a method of depositing a thin film on a pattern structure of a semiconductor substrate, the method including (a) supplying a source gas; (b) supplying a reactive gas; and (c) supplying plasma, wherein the steps (a), (b), and (c) are sequentially repeated on the semiconductor substrate within a reaction space until a desired thickness is obtained, and a frequency of the plasma is a high frequency of 60 MHz or greater.

公开(公告)号：US10262854B2

公开(公告)日：2019-04-16

申请号：US15706435

申请日：2017-09-15

Applicant: ASM IP Holding B.V.

Inventor： Shang Chen ,  Viljami Pore ,  Ryoko Yamada ,  Antti Juhani Niskanen

IPC: H01L21/02 ,  C23C16/04 ,  C23C16/34 ,  C23C16/455

Abstract: Methods and precursors for forming silicon nitride films are provided. In some embodiments, silicon nitride can be deposited by atomic layer deposition (ALD), such as plasma enhanced ALD. In some embodiments, deposited silicon nitride can be treated with a plasma treatment. The plasma treatment can be a nitrogen plasma treatment. In some embodiments the silicon precursors for depositing the silicon nitride comprise an iodine ligand. The silicon nitride films may have a relatively uniform etch rate for both vertical and the horizontal portions when deposited onto three-dimensional structures such as FinFETS or other types of multiple gate FETs. In some embodiments, various silicon nitride films of the present disclosure have an etch rate of less than half the thermal oxide removal rate with diluted HF (0.5%). In some embodiments, a method for depositing silicon nitride films comprises a multi-step plasma treatment.

公开(公告)号：US20190109037A1

公开(公告)日：2019-04-11

申请号：US16210440

申请日：2018-12-05

Applicant: ASM IP HOLDING B.V.

Inventor： Michael Halpin

IPC: H01L21/687 ,  F16D1/12 ,  F16D1/033

Abstract: The invention is directed to an alignment assembly for changing the relative position of a plate of a pedestal assembly with respect to a processing chamber of a reactor. The alignment assembly is connected at a first end to a riser shaft of the heating assembly and at a second end to a drive shaft. One or more portions of the alignment assembly may be selectively axially rotated or laterally moved change the relative position of the plate with respect to the processing chamber as desired.