公开(公告)号：US10290639B2

公开(公告)日：2019-05-14

申请号：US15702243

申请日：2017-09-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang

IPC: H01L21/8238 ,  H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L23/535 ,  H01L21/285

Abstract: A method of forming a VNW SRAM device with a vertical cross-couple/PD/PU contact landed on a PD/PU gate and a bottom nRX and pRX interface and the resulting device are provided. Embodiments include forming a first and a second bottom nRX and pRX over an NW upon a p-sub, the pRX formed between the nRX; forming fins over the first nRX, the first pRX, the second pRX, and over the second nRX; forming a first GAA perpendicular to and over the second pRX and nRX, a second GAA perpendicular to and over the first nRX and pRX, a third GAA perpendicular to and over a portion the first nRX, and a fourth GAA perpendicular to and over a portion of the second nRX; and forming a first and a second metal gate contact on the first GAA, nRX, and pRX and on the second GAA, pRX, and nRX, respectively.

公开(公告)号：US10276560B2

公开(公告)日：2019-04-30

申请号：US15638850

申请日：2017-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bingwu Liu ,  Hui Zang

IPC: H01L27/06 ,  H01L21/8234

Abstract: Structures for a passive device of an integrated circuits and associated fabrication methods. A semiconductor substrate having raised fins and an dielectric isolation layer between the fins is formed. An etch stop layer is formed over the dielectric isolation layer between fins of a passive device. An interlayer dielectric layer is formed over the fins and etch stop layer. The interlayer dielectric layer is selectively etched to form an opening for conductive contact to the fins, where the etch stop layer prevents etching of the dielectric isolation layer. A conductive contact is formed to contact the plurality of fins, with the conductive contact terminating at the etch stop layer.

公开(公告)号：US10263122B1

公开(公告)日：2019-04-16

申请号：US15828386

申请日：2017-11-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Ruilong Xie ,  Tek Po Rinus Lee ,  Lars Liebmann

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/808 ,  H01L29/788 ,  H01L27/088 ,  H01L21/302 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/3065

Abstract: A method, apparatus, and manufacturing system are disclosed herein for a vertical field effect transistor including a gate contact patterned in a self-aligned process. In one embodiment, we disclose a semiconductor device, including a semiconductor substrate and a first vertical field effect transistor (vFET) including a bottom source/drain (S/D) region disposed on the semiconductor substrate; a fin disposed above the bottom S/D region; a top source/drain (S/D) region disposed above the fin and having a top surface; and a gate having a top surface higher than the top surface of the top S/D region. A gate contact may be formed over the gate.

公开(公告)号：US10243059B2

公开(公告)日：2019-03-26

申请号：US15994614

申请日：2018-05-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Srikanth Balaji Samavedan ,  Manfred Eller ,  Min-hwa Chi ,  Hui Zang

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/306 ,  H01L21/308

Abstract: A method of reducing parasitic capacitance includes providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate with fin(s) thereon, the fin(s) having at least two dummy transistors integrated therewith and separated by a dielectric region, the dummy transistors including dummy gates with spacers and gate caps, the fin(s) having ends tucked by the dummy gates. The method further includes removing the dummy gates and gate caps, resulting in gate trenches, protecting area(s) of the structure during fabrication process(es) where source/drain parasitic capacitance may occur, and forming air-gaps at a bottom portion of unprotected gate trenches to reduce parasitic capacitance. The resulting semiconductor structure includes a semiconductor substrate with fin(s) thereon, FinFET(s) integral with the fin(s), the FinFET(s) including a gate electrode, a gate liner lining the gate electrode, and air-gap(s) in gate trench(es) of the FinFET(s), reducing parasitic capacitance by at least about 75 percent as compared to no air-gaps.

公开(公告)号：US20190088767A1

公开(公告)日：2019-03-21

申请号：US15709500

申请日：2017-09-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Lars Liebmann ,  Hui Zang ,  Steven Bentley

IPC: H01L29/66

Abstract: Disclosed is a method of forming an integrated circuit (IC) that incorporates multiple vertical field effect transistors (VFETs) (e.g., in a VFET array). In the method, self-aligned gates for each pair of VFETs and a self-aligned gate extension for contacting those self-aligned gates are essentially simultaneously formed such that the gates wrap around a pair of semiconductor fins, which are in end-to-end alignment, and such that the gate extension fills the space between adjacent ends of those semiconductor fins. By forming self-aligned gates and a self-aligned gate extension for a pair of VFETs, the method avoids the need for lithographically patterning extension cut isolation regions between adjacent pairs of VFETs in a VFET array. Thus, the method enables implementation of VFET array designs with a reduced fin pitch without incurring defects caused, for example, by overlay errors. Also disclosed herein is an IC formed according to the method.

公开(公告)号：US10236213B1

公开(公告)日：2019-03-19

申请号：US15917940

申请日：2018-03-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shesh M. Pandey ,  Jiehui Shu ,  Hui Zang ,  Laertis Economikos

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/311

Abstract: A gate cut structure for finFETs, and a related method, are disclosed. The gate cut structure separates and electrically isolates an end of a first metal gate conductor of a first finFET from an end of a second metal gate conductor of a second finFET. The gate cut structure includes a body contacting the end of the first and second metal gate conductors. A liner spacer separates a lower portion of the body from an interlayer dielectric (ILD), and an upper portion of the body contacts the ILD. During formation, the liner spacer allows for a larger gate cut opening to be used to allow quality cleaning of the gate cut opening, but also reduction in size of the spacing between metal gate conductor ends of the finFETs. In one example, the body may have a lower portion having a width less than an upper portion thereof.

公开(公告)号：US10230000B2

公开(公告)日：2019-03-12

申请号：US15671605

申请日：2017-08-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Emilie Bourjot ,  Daniel Chanemougame ,  Tek Po Rinus Lee ,  Ruilong Xie ,  Hui Zang

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/423

Abstract: Methods and structures that include a vertical-transport field-effect transistor. A semiconductor fin is formed that projects from a first source/drain region. A second source/drain region is spaced vertically along the semiconductor fin from the first source/drain region. A gate stack is arranged between the second source/drain region and the first source/drain region. A spacer is formed adjacent to a sidewall of the second source/drain region. A first contact is connected with a top surface of the second source/drain region, a second contact is connected with a top surface of the first source/drain region, and a third contact is connected with a top surface of the gate stack. The spacer is arranged between the second source/drain region and the second contact or between the second source/drain region and the third contact.

公开(公告)号：US10211315B2

公开(公告)日：2019-02-19

申请号：US15654165

申请日：2017-07-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Haigou Huang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417

Abstract: Structures for a vertical-transport field-effect transistor and methods for forming a structure for a vertical-transport field-effect transistor. A semiconductor fin is formed on a source/drain region. A gate stack is deposited that coats the semiconductor fin and a contact landing area of the source/drain region adjacent to the semiconductor fin. The gate stack is patterned to remove the gate stack from the contact landing area and to form a gate electrode having a section adjacent to the contact landing area. The section of the gate electrode is laterally recessed to form a cavity, and a dielectric spacer is formed in the cavity.

公开(公告)号：US20190051733A1

公开(公告)日：2019-02-14

申请号：US16009331

申请日：2018-06-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L21/76897 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823487 ,  H01L29/0847 ,  H01L29/42376 ,  H01L29/66666 ,  H01L29/7827

Abstract: Disclosed are embodiments of a semiconductor structure that includes a vertical field effect transistor (VFET). The VFET has a fin-shaped body that includes a semiconductor fin and an isolation fin. The semiconductor fin extends vertically between lower and upper source/drain regions. The isolation fin is adjacent to and in end-to-end alignment with the semiconductor fin. The VFET gate has a main section that wraps around an outer end and opposing sidewalls of the semiconductor fin and an extension section that extends from the main section along at least the opposing sidewalls of a lower portion the isolation fin and, optionally, around an outer end of that lower portion. A gate contact lands on the isolation fin and extends along the opposing sidewalls and, optionally, the outer end of the isolation fin down to the extension section. Also disclosed are method embodiments for forming these structures.

公开(公告)号：US10204904B2

公开(公告)日：2019-02-12

申请号：US15592172

申请日：2017-05-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Rinus Tek Po Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/764

Abstract: A method, apparatus and system are disclosed herein for a finFET device having an air gap spacer and/or a tapered bottom dielectric spacer for reducing parasitic capacitance. A first source/drain (S/D) region is formed on a substrate. A set of fin structures are formed above the first S/D region. A gate region is formed above the first S/D region and adjacent at least a portion of the fin structures. A space for an air gap is formed above the gate region. A top epitaxial (EPI) feature is formed extending over the space for the air gap, thereby forming an air gap spacer between the top epitaxial feature and the gate region.