METHOD FOR SENDING A SOUNDING REFERENCE SIGNAL OF UPLINK CHANNEL IN A TIME DIVISION DUPLEX SYSTEM
    381.
    发明申请
    METHOD FOR SENDING A SOUNDING REFERENCE SIGNAL OF UPLINK CHANNEL IN A TIME DIVISION DUPLEX SYSTEM 有权
    用于在时分双工系统中发送上行链路信道的参考信号的方法

    公开(公告)号:US20110013546A1

    公开(公告)日:2011-01-20

    申请号:US12920958

    申请日:2009-06-02

    CPC classification number: H04L5/0007 H04L5/005 H04L5/0091 H04W72/044

    Abstract: A method for sending a sounding reference signal (SRS) of uplink channel in a time division duplex system is provided, a terminal calculates the parameters of the resource for sending an SRS in an uplink pilot time slot (UpPTS) according to the configuration information related to the sounding reference signal (SRS) of the uplink channel, the parameters include the frequency domain start position of the resource, and then the SRS is sent over the resource; wherein when the frequency domain start position of the resource is calculated, it is necessary to determine the index of the first sub-carrier in the maximum SRS bandwidth; the terminal determines the index according to the frequency domain position of one PRACH or that of more PRACHs in the uplink pilot time slots, when the PRACH includes the sub-carrier at the lower boundary of the system bandwidth, the upper boundary of the system bandwidth is used as the end position of the maximum SRS bandwidth and the start position of the maximum SRS bandwidth is calculated; and when the PRACH includes the sub-carrier at the upper boundary of the system bandwidth, the lower boundary of the system bandwidth is used as the start position of the maximum SRS bandwidth, and then the index is determined through the start position of the maximum SRS bandwidth plus the offset parameter configured for the terminal. With the sending position of the maximum SRS bandwidth in the UpPTS, which is obtained by the method of the present invention, the interference between the SRS signal and the PARCH can be avoided, and it is possible to implement the channel sounding for more bandwidth.

    Abstract translation: 提供了一种用于在时分双工系统中发送上行链路信道的探测参考信号(SRS)的方法,终端根据相关配置信息计算上行链路导频时隙(UpPTS)中发送SRS的资源参数 到上行链路信道的探测参考信号(SRS),参数包括资源的频域起始位置,然后通过资源发送SRS; 其中,当计算出资源的频域起始位置时,需要确定最大SRS带宽中的第一子载波的索引; 当PRACH包括系统带宽下边界的子载波时,终端根据一个PRACH的频域位置或上行导频时隙中的更多PRACH的频域确定索引,系统带宽的上限 用作最大SRS带宽的最终位置,并计算最大SRS带宽的起始位置; 并且当PRACH在系统带宽的上边界处包括子载波时,系统带宽的下边界被用作最大SRS带宽的起始位置,然后通过最大值的起始位置确定索引 SRS带宽加上为终端配置的偏移参数。 通过本发明的方法获得的UPPTS中的最大SRS带宽的发送位置可以避免SRS信号与PARCH之间的干扰,并且可以实现更多带宽的信道探测。

    METHOD FOR ALLOCATING PHYSICAL HYBRID ARQ INDICATOR CHANNELS
    382.
    发明申请
    METHOD FOR ALLOCATING PHYSICAL HYBRID ARQ INDICATOR CHANNELS 有权
    分配物理混合ARQ指示器通道的方法

    公开(公告)号:US20110007674A1

    公开(公告)日:2011-01-13

    申请号:US12919665

    申请日:2009-02-13

    Abstract: The present disclosure provides a method for allocating physical hybrid ARQ indicator channels, which is used for sending indication information corresponding to multiple uplink sub-frames in the same downlink sub-frame in a TDD system. The method includes: in the TDD system, through an index of a physical resource block where uplink data resides as well as an index of an uplink sub-frame where the uplink data resides, determining an index of a physical hybrid ARQ indicator channel group where a physical hybrid ARQ indicator channel in an downlink sub-frame resides and an intra-group index of the physical hybrid ARQ indicator channel in the physical hybrid ARQ indicator channel group according to an indexing rule, and further determining an index of the physical hybrid ARQ indicator channel by using the index of the physical hybrid ARQ indicator channel group and the intra-group index. According to implicit mapping, the method of the present disclosure implements the allocation of the physical hybrid ARQ indicator channels over which the downlink indication messages corresponding to each uplink sub-frame are transmitted, thereby being capable of overcoming the problem potentially present in existing technologies that multiple indication messages reside on the same physical hybrid ARQ indicator channel.

    Abstract translation: 本公开提供了一种用于分配物理混合ARQ指示符信道的方法,用于在TDD系统中的相同下行链路子帧中发送对应于多个上行链路子帧的指示信息。 该方法包括:在TDD系统中,通过上行链路数据所在的物理资源块的索引以及上行链路数据所在的上行链路子帧的索引,确定物理混合ARQ指示符信道组的索引,其中 根据索引规则,下行子帧中的物理混合ARQ指示符信道驻留在物理混合ARQ指示符信道组中的物理混合ARQ指示符信道的组内索引,并进一步确定物理混合ARQ指示符信道的索引 指标通道采用物理混合ARQ指标通道组索引和组内指标。 根据隐式映射,本公开的方法实现物理混合ARQ指示符信道的分配,通过该配置,发送与每个上行链路子帧相对应的下行链路指示消息,从而能够克服现有技术中潜在存在的问题, 多个指示消息驻留在相同的物理混合ARQ指示符通道上。

    Method and Apparatus for Sequencing ZC Sequences of a Random Access Channel
    383.
    发明申请
    Method and Apparatus for Sequencing ZC Sequences of a Random Access Channel 有权
    用于排序随机接入信道的ZC序列的方法和装置

    公开(公告)号:US20100309993A1

    公开(公告)日:2010-12-09

    申请号:US12864653

    申请日:2008-12-02

    Abstract: The present invention provides a method and apparatus for sequencing ZC sequences of a random access channel. The method comprises: setting α as a logical index of each ZC sequence, and u as a physical index of said each ZC sequence, wherein 1≦u≦N−1, 0≦α≦N−2, and N is the length of said each ZC sequence; establishing a mapping relationship between the logical index and the physical index: u=N/2 is taken as a symmetry axis, α is mapped to u in a manner of longitudinal symmetry, and on the upper side of the symmetry axis, u monotonously decreases or increases, while on the lower side of the symmetry axis, u monotonously increases or decreases. This method ensures that the PRACHs of the UEs using different sequences in a same cell have similar coverage, thus the flexibility of cell planning is increased.

    Abstract translation: 本发明提供了一种用于对随机接入信道的ZC序列进行排序的方法和装置。 该方法包括:将α设置为每个ZC序列的逻辑索引,u作为所述每个ZC序列的物理索引,其中1≦̸ u≦̸ N-1,0≦̸α≦̸ N-2和N是 说每个ZC序列; 建立逻辑索引与物理指标之间的映射关系:u = N / 2作为对称轴,α以纵向对称方式映射到u,在对称轴的上侧,u单调减小 或增加,而在对称轴的下侧,u单调增加或减少。 该方法确保在同一小区中使用不同序列的UE的PRACH具有相似的覆盖,从而增加小区规划的灵活性。

    Reversed T-shaped finfet
    384.
    发明授权
    Reversed T-shaped finfet 失效
    反转T形finfet

    公开(公告)号:US07541267B1

    公开(公告)日:2009-06-02

    申请号:US11765611

    申请日:2007-06-20

    CPC classification number: H01L29/785 H01L29/42392 H01L29/66795 H01L29/7842

    Abstract: A method includes forming a first rectangular mesa from a layer of semiconducting material and forming a first dielectric layer around the first mesa. The method further includes forming a first rectangular mask over a first portion of the first mesa leaving an exposed second portion of the first mesa and etching the exposed second portion of the first mesa to produce a reversed T-shaped fin from the first mesa.

    Abstract translation: 一种方法包括从半导体材料层形成第一矩形台面并在第一台面周围形成第一介电层。 该方法还包括在第一台面的第一部分上形成第一矩形掩模,离开第一台面的暴露的第二部分并蚀刻第一台面的暴露的第二部分以从第一台面产生反向的T形翅片。

    Scanning laser thermal annealing
    385.
    发明授权
    Scanning laser thermal annealing 有权
    扫描激光热退火

    公开(公告)号:US07351638B1

    公开(公告)日:2008-04-01

    申请号:US10021782

    申请日:2001-12-18

    CPC classification number: H01L21/268 H01L21/26513 H01L29/6659

    Abstract: A method of manufacturing a semiconductor device includes forming a gate electrode over a substrate, implanting dopants into the substrate and activating the dopants using laser thermal annealing. During annealing, the laser and substrate are moved relative to one another, and the movement of the laser and the substrate relative to one another does not pause between and during activating one portion of the source/drain regions and activating another portion of the source/drain regions. Each pulse from the laser can respectively irradiate different portions of the source/drain regions, and a spot area of the laser is less than 50 millimeter2.

    Abstract translation: 一种制造半导体器件的方法包括在衬底上形成栅电极,将掺杂剂注入到衬底中并使用激光热退火激活掺杂剂。 在退火期间,激光器和衬底相对于彼此移动,并且激光器和衬底相对于彼此的运动在激活源极/漏极区域的一部分之间和在激活源极/漏极区域的另一部分之间不间断, 漏区。 来自激光器的每个脉冲可以分别照射源极/漏极区域的不同部分,并且激光器的斑点面积小于50毫米2。

    SRAM formation using shadow implantation
    386.
    发明授权
    SRAM formation using shadow implantation 有权
    使用阴影植入的SRAM形成

    公开(公告)号:US07298007B1

    公开(公告)日:2007-11-20

    申请号:US11171399

    申请日:2005-07-01

    Abstract: A memory device includes multiple fins formed adjacent to one another, a source region, a drain region, a gate, a wordline, and a bitline contact. At least one of the multiple fins is doped with a first type of impurities and at least one other one of the fins is doped with a second type of impurities. The source region is formed at one end of each of the fins and the drain region is formed at an opposite end of each of the fins. The gate is formed over two of the multiple fins, the wordline is formed over each of the multiple fins, and a bitline contact is formed adjacent at least one of the multiple fins.

    Abstract translation: 存储器件包括彼此相邻形成的多个鳍,源极区,漏极区,栅极,字线和位线接触。 多个翅片中的至少一个被掺杂有第一类型的杂质,并且至少另外一个翅片掺杂有第二类型的杂质。 源区域形成在每个散热片的一端,并且漏极区域形成在每个散热片的相对端。 栅极形成在多个散热片的两个之上,字线形成在多个散热片的每一个上,并且与多个散热片中的至少一个相邻地形成有位线接触。

    Tri-gate and gate around MOSFET devices and methods for making same
    388.
    发明授权
    Tri-gate and gate around MOSFET devices and methods for making same 有权
    围绕MOSFET器件的三栅极和栅极及其制造方法

    公开(公告)号:US07259425B2

    公开(公告)日:2007-08-21

    申请号:US10348911

    申请日:2003-01-23

    CPC classification number: H01L29/785 H01L29/42384 H01L29/66545 H01L29/66795

    Abstract: A triple gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin structure, a first gate formed adjacent a first side of the fin structure, a second gate formed adjacent a second side of the fin structure opposite the first side, and a top gate formed on top of the fin structure. A gate around MOSFET includes multiple fins, a first sidewall gate structure formed adjacent one of the fins, a second sidewall gate structure formed adjacent another one of the fins, a top gate structure formed on one or more of the fins, and a bottom gate structure formed under one or more of the fins.

    Abstract translation: 三栅极金属氧化物半导体场效应晶体管(MOSFET)包括翅片结构,邻近翅片结构的第一侧形成的第一栅极,与第一侧相对的翅片结构的第二侧附近形成的第二栅极,以及 形成在鳍结构顶部的顶门。 MOSFET周围的栅极包括多个散热片,邻近其中一个翅片形成的第一侧壁栅极结构,邻近另一个鳍片形成的第二侧壁栅极结构,形成在一个或多个翅片上的顶部栅极结构,以及底部栅极 在一个或多个翅片下形成的结构。

    Double gate semiconductor device having a metal gate
    389.
    发明授权
    Double gate semiconductor device having a metal gate 有权
    具有金属栅极的双栅极半导体器件

    公开(公告)号:US07256455B2

    公开(公告)日:2007-08-14

    申请号:US10720166

    申请日:2003-11-25

    CPC classification number: H01L29/785 H01L29/42384 H01L29/66545 H01L29/66795

    Abstract: A semiconductor device may include a substrate, an insulating layer formed on the substrate and a conductive fin formed on the insulating layer. The conductive fin may include a number of side surfaces and a top surface. The semiconductor device may also include a source region formed on the insulating layer adjacent a first end of the conductive fin and a drain region formed on the insulating layer adjacent a second end of the conductive fin. The semiconductor device may further include a metal gate formed on the insulating layer adjacent the conductive fin in a channel region of the semiconductor device.

    Abstract translation: 半导体器件可以包括衬底,形成在衬底上的绝缘层和形成在绝缘层上的导电鳍。 导电翅片可以包括多个侧表面和顶表面。 半导体器件还可以包括形成在与导电鳍片的第一端相邻的绝缘层上的源极区域和形成在与导电鳍片的第二端相邻的绝缘层上的漏极区域。 半导体器件还可以包括在半导体器件的沟道区域中形成在与绝缘层相邻的导电鳍片上的金属栅极。

    DOPED STRUCTURE FOR FINFET DEVICES
    390.
    发明申请
    DOPED STRUCTURE FOR FINFET DEVICES 有权
    FINFET器件的DOPED结构

    公开(公告)号:US20070141791A1

    公开(公告)日:2007-06-21

    申请号:US11677404

    申请日:2007-02-21

    Inventor: Ming-Ren Lin Bin Yu

    Abstract: A semiconductor device includes a substrate and an insulating layer on the substrate. The semiconductor device also includes a fin structure formed on the insulating layer, where the fin structure includes first and second side surfaces, a dielectric layer formed on the first and second side surfaces of the fin structure, a first gate electrode formed adjacent the dielectric layer on the first side surface of the fin structure, a second gate electrode formed adjacent the dielectric layer on the second side surface of the fin structure, and a doped structure formed on an upper surface of the fin structure in the channel region of the semiconductor device.

    Abstract translation: 半导体器件包括衬底和衬底上的绝缘层。 半导体器件还包括形成在绝缘层上的翅片结构,其中鳍结构包括第一和第二侧表面,形成在鳍结构的第一和第二侧表面上的电介质层,形成在电介质层附近的第一栅电极 在翅片结构的第一侧表面上形成与鳍结构的第二侧表面上的电介质层相邻的第二栅电极,以及在半导体器件的沟道区中形成在鳍结构的上表面上的掺杂结构 。

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