Abstract:
A method for sending a sounding reference signal (SRS) of uplink channel in a time division duplex system is provided, a terminal calculates the parameters of the resource for sending an SRS in an uplink pilot time slot (UpPTS) according to the configuration information related to the sounding reference signal (SRS) of the uplink channel, the parameters include the frequency domain start position of the resource, and then the SRS is sent over the resource; wherein when the frequency domain start position of the resource is calculated, it is necessary to determine the index of the first sub-carrier in the maximum SRS bandwidth; the terminal determines the index according to the frequency domain position of one PRACH or that of more PRACHs in the uplink pilot time slots, when the PRACH includes the sub-carrier at the lower boundary of the system bandwidth, the upper boundary of the system bandwidth is used as the end position of the maximum SRS bandwidth and the start position of the maximum SRS bandwidth is calculated; and when the PRACH includes the sub-carrier at the upper boundary of the system bandwidth, the lower boundary of the system bandwidth is used as the start position of the maximum SRS bandwidth, and then the index is determined through the start position of the maximum SRS bandwidth plus the offset parameter configured for the terminal. With the sending position of the maximum SRS bandwidth in the UpPTS, which is obtained by the method of the present invention, the interference between the SRS signal and the PARCH can be avoided, and it is possible to implement the channel sounding for more bandwidth.
Abstract:
The present disclosure provides a method for allocating physical hybrid ARQ indicator channels, which is used for sending indication information corresponding to multiple uplink sub-frames in the same downlink sub-frame in a TDD system. The method includes: in the TDD system, through an index of a physical resource block where uplink data resides as well as an index of an uplink sub-frame where the uplink data resides, determining an index of a physical hybrid ARQ indicator channel group where a physical hybrid ARQ indicator channel in an downlink sub-frame resides and an intra-group index of the physical hybrid ARQ indicator channel in the physical hybrid ARQ indicator channel group according to an indexing rule, and further determining an index of the physical hybrid ARQ indicator channel by using the index of the physical hybrid ARQ indicator channel group and the intra-group index. According to implicit mapping, the method of the present disclosure implements the allocation of the physical hybrid ARQ indicator channels over which the downlink indication messages corresponding to each uplink sub-frame are transmitted, thereby being capable of overcoming the problem potentially present in existing technologies that multiple indication messages reside on the same physical hybrid ARQ indicator channel.
Abstract:
The present invention provides a method and apparatus for sequencing ZC sequences of a random access channel. The method comprises: setting α as a logical index of each ZC sequence, and u as a physical index of said each ZC sequence, wherein 1≦u≦N−1, 0≦α≦N−2, and N is the length of said each ZC sequence; establishing a mapping relationship between the logical index and the physical index: u=N/2 is taken as a symmetry axis, α is mapped to u in a manner of longitudinal symmetry, and on the upper side of the symmetry axis, u monotonously decreases or increases, while on the lower side of the symmetry axis, u monotonously increases or decreases. This method ensures that the PRACHs of the UEs using different sequences in a same cell have similar coverage, thus the flexibility of cell planning is increased.
Abstract:
A method includes forming a first rectangular mesa from a layer of semiconducting material and forming a first dielectric layer around the first mesa. The method further includes forming a first rectangular mask over a first portion of the first mesa leaving an exposed second portion of the first mesa and etching the exposed second portion of the first mesa to produce a reversed T-shaped fin from the first mesa.
Abstract:
A method of manufacturing a semiconductor device includes forming a gate electrode over a substrate, implanting dopants into the substrate and activating the dopants using laser thermal annealing. During annealing, the laser and substrate are moved relative to one another, and the movement of the laser and the substrate relative to one another does not pause between and during activating one portion of the source/drain regions and activating another portion of the source/drain regions. Each pulse from the laser can respectively irradiate different portions of the source/drain regions, and a spot area of the laser is less than 50 millimeter2.
Abstract:
A memory device includes multiple fins formed adjacent to one another, a source region, a drain region, a gate, a wordline, and a bitline contact. At least one of the multiple fins is doped with a first type of impurities and at least one other one of the fins is doped with a second type of impurities. The source region is formed at one end of each of the fins and the drain region is formed at an opposite end of each of the fins. The gate is formed over two of the multiple fins, the wordline is formed over each of the multiple fins, and a bitline contact is formed adjacent at least one of the multiple fins.
Abstract:
Multiple semiconductor devices are formed with different threshold voltages. According to one exemplary implementation, first and second semiconductor devices are formed and doped differently, resulting in different threshold voltages for the first and second semiconductor devices.
Abstract:
A triple gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin structure, a first gate formed adjacent a first side of the fin structure, a second gate formed adjacent a second side of the fin structure opposite the first side, and a top gate formed on top of the fin structure. A gate around MOSFET includes multiple fins, a first sidewall gate structure formed adjacent one of the fins, a second sidewall gate structure formed adjacent another one of the fins, a top gate structure formed on one or more of the fins, and a bottom gate structure formed under one or more of the fins.
Abstract:
A semiconductor device may include a substrate, an insulating layer formed on the substrate and a conductive fin formed on the insulating layer. The conductive fin may include a number of side surfaces and a top surface. The semiconductor device may also include a source region formed on the insulating layer adjacent a first end of the conductive fin and a drain region formed on the insulating layer adjacent a second end of the conductive fin. The semiconductor device may further include a metal gate formed on the insulating layer adjacent the conductive fin in a channel region of the semiconductor device.
Abstract:
A semiconductor device includes a substrate and an insulating layer on the substrate. The semiconductor device also includes a fin structure formed on the insulating layer, where the fin structure includes first and second side surfaces, a dielectric layer formed on the first and second side surfaces of the fin structure, a first gate electrode formed adjacent the dielectric layer on the first side surface of the fin structure, a second gate electrode formed adjacent the dielectric layer on the second side surface of the fin structure, and a doped structure formed on an upper surface of the fin structure in the channel region of the semiconductor device.