公开(公告)号：US12197533B2

公开(公告)日：2025-01-14

申请号：US17214784

申请日：2021-03-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Pramod Vasant Argade ,  Swapnil P. Sakharshete ,  Maxim V. Kazakov ,  Alexander M. Potapov

IPC: G06F17/16 ,  G06F7/523 ,  G06F7/544 ,  G06F7/556

Abstract: A processing device is provided which comprises memory configured to store data and a processor configured to receive a portion of data of a first matrix comprising a first plurality of elements and receive a portion of data of a second matrix comprising a second plurality of elements. The processor is also configured to determine values for a third matrix by dropping a number of products from products of pairs of elements of the first and second matrices based on approximating the products of the pairs of elements as a sum of the exponents of the pairs of elements and performing matrix multiplication on remaining products of the pairs of elements of the first and second matrices.

公开(公告)号：US12190174B2

公开(公告)日：2025-01-07

申请号：US16425881

申请日：2019-05-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexandru Dutu ,  Sergey Blagodurov ,  Anthony T. Gutierrez ,  Matthew D. Sinclair ,  David A. Wood ,  Bradford M. Beckmann

IPC: G06F9/52 ,  G06F9/48 ,  G06F11/30 ,  G06F11/34

Abstract: A technique for synchronizing workgroups is provided. Multiple workgroups execute a wait instruction that specifies a condition variable and a condition. A workgroup scheduler stops execution of a workgroup that executes a wait instruction and an advanced controller begins monitoring the condition variable. In response to the advanced controller detecting that the condition is met, the workgroup scheduler determines whether there is a high contention scenario, which occurs when the wait instruction is part of a mutual exclusion synchronization primitive and is detected by determining that there is a low number of updates to the condition variable prior to detecting that the condition has been met. In a high contention scenario, the workgroup scheduler wakes up one workgroup and schedules another workgroup to be woken up at a time in the future. In a non-contention scenario, more than one workgroup can be woken up at the same time.

公开(公告)号：US12189953B2

公开(公告)日：2025-01-07

申请号：US17956417

申请日：2022-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Jagadish B. Kotra ,  John Kalamatianos

IPC: G06F12/00 ,  G06F3/06

Abstract: Methods, devices, and systems for retrieving information based on cache miss prediction. It is predicted, based on a history of cache misses at a private cache, that a cache lookup for the information will miss a shared victim cache. A speculative memory request is enabled based on the prediction that the cache lookup for the information will miss the shared victim cache. The information is fetched based on the enabled speculative memory request.

公开(公告)号：US12189534B2

公开(公告)日：2025-01-07

申请号：US17564474

申请日：2021-12-29

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Saurabh Sharma ,  Hashem Hashemi ,  Paavo Pessi ,  Mika Tuomi ,  Gianpaolo Tommasi ,  Jeremy Lukacs ,  Guennadi Riguer

IPC: G06F9/46 ,  G06F9/48 ,  G06F12/0855

Abstract: A processing system divides successive dispatches of work items into portions. The successive dispatches are separated from each other by barriers, each barrier indicating that the work items of the previous dispatch must complete execution before work items of a subsequent dispatch can begin execution. In some embodiments, the processing system interleaves execution of portions of a first dispatch with portions of subsequent dispatches that consume data produced by the first dispatch. The processing system thereby reduces the amount of data written to the local cache by a producer dispatch while preserving data locality for a subsequent consumer (or consumer/producer) dispatch and facilitating processing efficiency.

公开(公告)号：US12189530B2

公开(公告)日：2025-01-07

申请号：US18621799

申请日：2024-03-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul J. Moyer

IPC: G06F12/08 ,  G06F12/0802

Abstract: Disclosed is a system and method for use in a cache for suppressing modification of cache line. The system and method includes a processor and a memory operating cooperatively with a cache controller. The memory includes a coherence directory stored within a cache created to track at least one cache line in the cache via the cache controller. The processor instructs a cache controller to store a first data in a cache line in the cache. The cache controller tags the cache line based on the first data. The processor instructs the cache controller to store a second data in the cache line in the cache causing eviction of the first data from the cache line. The processor compares based on the tagging the first data and the second data and suppresses modification of the cache line based on the comparing of the first data and the second data.

公开(公告)号：US20250006496A1

公开(公告)日：2025-01-02

申请号：US18345233

申请日：2023-06-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： CHIA CHUN MIAO ,  SUNGJUN IM ,  HIMANSHU A BAL

IPC: H01L21/033 ,  H01L21/304 ,  H01L23/367

Abstract: A method for forming a lid of a semiconductor assembly includes applying a mask to a surface of the lid to leave an area of the lid including a pedestal and wider than the pedestal included in the lid exposed. The method applies a thermally conductive material to the area of the surface of the lid that is exposed and removes at least a portion of the thermally conductive material from the surface of the lid.

公开(公告)号：US20250006290A1

公开(公告)日：2025-01-02

申请号：US18343377

申请日：2023-06-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Nehal Patel

IPC: G11C29/36 ,  G11C29/12 ,  G11C29/56

Abstract: Some implementations provide systems methods and devices for integrated circuit self-test. The integrated circuit includes interface circuitry configured to read test data and to write the test data into memory of the integrated circuit. The integrated circuit also includes test circuitry configured to test the interface circuitry based on the test data written into memory of the integrated circuit. Some implementations provide an integrated circuit configured for storing and reading data. The integrated circuit includes circuitry configured to write or read a first portion of data to or from a first memory via BIST circuitry of the first memory until a first BIST counter saturates. The integrated circuit also includes circuitry configured to write or read a second portion of the data to or from a second memory via BIST circuitry of the second memory until a second BIST counter saturates.

公开(公告)号：US20250006246A1

公开(公告)日：2025-01-02

申请号：US18344812

申请日：2023-06-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell Schreiber ,  Clinton Harold Parker

IPC: G11C11/408 ,  G11C11/4076 ,  H03K19/017

Abstract: An apparatus and method for both reducing power consumption and increasing read access stability of a memory array. An integrated circuit includes a memory array with memory bit cells arranged as multiple rows and multiple columns. The array also includes multiple word line driver circuits configured to generate a corresponding word line for multiple rows. The array includes an underdrive circuit configured to adjust, via a configurable resistor-capacitor circuit, a rate of change of a voltage level of a word line. The configurable resistor-capacitor circuit controls the store data rate of the charging of the selected word line and allows the selected word line to charge to the power supply voltage. The configurable resistor-capacitor circuit controls the rate of charging without creating a direct current path between the power supply voltage and the ground reference level that would increase power consumption.

公开(公告)号：US20250005929A1

公开(公告)日：2025-01-02

申请号：US18217250

申请日：2023-06-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Jonathan Philip Bonsor-Matthews

IPC: G06V20/40 ,  G06V10/25 ,  G06V10/26

Abstract: A portable electronic device includes a video encoder. The video encoder is configured to receive a video frame. Responsive to the video frame including at least one of a salient object or a region of interest, the video encoder is further configured to partition the video frame into one or more tiles based on a location of the at least one of the salient object or the region of interest.

公开(公告)号：US20250004943A1

公开(公告)日：2025-01-02

申请号：US18345974

申请日：2023-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Edgar Munoz ,  Chintan S. Patel ,  Gregg Donley ,  Vydhyanathan Kalyanasundharam

IPC: G06F12/0802

Abstract: The disclosed device includes a first register that stores a cumulative delta value and a second register that stores an average cache hit rate. The device also includes a control circuit that calculates a cache hit rate and updates the cumulative delta value based on the cache hit rate and the average cache hit rate. The control circuit also updates the average cache hit rate based on the updated cumulative delta value, and can update a cache allocation policy based on the updated average cache hit rate. Various other methods, systems, and computer-readable media are also disclosed.