公开(公告)号：US20110273215A1

公开(公告)日：2011-11-10

申请号：US12841096

申请日：2010-07-21

Applicant: Nitin GUPTA

Inventor： Nitin GUPTA

IPC: H03K3/00

CPC classification number: H03L7/199 ,  H03L7/0807 ,  H03L7/0812 ,  H03L7/091 ,  H04L7/0337

Abstract: In a method for recovery of a clock from a received digital data stream and an apparatus for recovering a clock from a received digital data stream, phase-shifted clock signals are generated from a receiver's clock. After selecting one of the phase-shifted clock signals, two other phase-shifted clock signals are determined. Depending on sample values taken at rising/falling edges of the three selected phase-shifted clock signals, counter values are increased and compared. The selection of phase-shifted clock signals and the steps of sampling the input digital data stream, comparing the values and increasing counter values, if required, are repeatedly performed until the comparison result of the counter values indicates that one of the latter determined phase-shifted clock signals strobes the received digital data stream in the centre of a bit period.

Abstract translation: 在从接收到的数字数据流中恢复时钟的方法和从接收的数字数据流中恢复时钟的装置中，从接收机的时钟产生相移的时钟信号。 在选择一个相移时钟信号之后，确定另外两个相移时钟信号。 根据在三个选定的相移时钟信号的上升沿/下降沿采集的采样值，增加和比较计数器值。 如果需要，相移时钟信号的选择和对输入数字数据流进行采样的步骤，比较值和增加计数器值，直到计数器值的比较结果指示后一个确定的相位时钟信号之一， 移位的时钟信号在接收到的位数周期的中心选通接收到的数字数据流。

公开(公告)号：US07999573B2

公开(公告)日：2011-08-16

申请号：US11649746

申请日：2007-01-03

Applicant: Rajesh Narwal ,  Manoj Kumar

Inventor： Rajesh Narwal ,  Manoj Kumar

IPC: H03K19/094

CPC classification number: H03K19/018528

Abstract: An embodiment of a low-to-high-level voltage translator is proposed. This translator translates the low voltage swing signals for the core into high voltage swing signals of the I/O blocks. This translator may be particularly useful for high-speed application where the difference between the core and the I/O supply voltage is very large, e.g., the core is working at 0.8V and the I/O is working at 3.6V or higher without little or no static power dissipation. The proposed translator may give improved transition times and propagation delays as compared to conventional translators. The proposed translator may also use less hardware in comparison to other such translators.

Abstract translation: 提出了一种低电平到高电平转换器的实施例。 该转换器将芯的低电压摆幅信号转换为I / O块的高电压摆幅信号。 这种转换器对于核心和I / O电源电压差异非常大的高速应用尤其有用，例如，核心工作在0.8V，I / O工作在3.6V或更高，而没有 很少或没有静态功耗。 与传统的翻译器相比，所提出的翻译器可以提供改进的转换时间和传播延迟。 与其他这样的翻译器相比，所提出的翻译器也可以使用较少的硬件。

公开(公告)号：US20110149668A1

公开(公告)日：2011-06-23

申请号：US12717019

申请日：2010-03-03

Applicant: Ashish KUMAR ,  Piyush Jain

Inventor： Ashish KUMAR ,  Piyush Jain

IPC: G11C7/00 ,  G11C5/14

CPC classification number: G11C11/412

Abstract: Memory devices and methods of operating a memory cell are disclosed in which a bitline can be grounded after charge sharing with an electrically floating ground line and before writing data to the memory cell. An electric potential of an upper power supply node of a memory cell can be lowered and an electric potential of a lower power supply node of the memory cell can be raised before writing data to the memory cell.

Abstract translation: 公开了存储器件和操作存储单元的方法，其中位线可以在与电浮动接地线电荷共享之后并且在将数据写入存储器单元之前接地。 可以降低存储单元的上电源节点的电位，并且可以在将数据写入存储单元之前提升存储单元的下电源节点的电位。

公开(公告)号：US20110142125A1

公开(公告)日：2011-06-16

申请号：US12819604

申请日：2010-06-21

Applicant: Subarna TRIPATHI ,  Emiliano Mario Piccinelli

Inventor： Subarna TRIPATHI ,  Emiliano Mario Piccinelli

IPC: H04N7/26

CPC classification number: H04N19/107 ,  H04N19/105 ,  H04N19/124 ,  H04N19/146 ,  H04N19/149 ,  H04N19/152 ,  H04N19/162 ,  H04N19/169 ,  H04N19/177 ,  H04N19/40

Abstract: A GOP-independent dynamic bit-rate controller system includes a user interface to receive one or more input parameters, a bit-rate controller and an encoder. The bit-rate controller regulates a bit-rate of an output bit-stream. The bit-rate controller includes multiple bit-rate modules to determine a bit-estimate and a quantization parameter, and a control module to calculate a convergence period based on the received input parameters and a frame rate. The control module selects a bit rate module based on the convergence period and the encoder generates the output bit-stream using the quantization parameter determined by the bit rate module.

Abstract translation: 独立于GOP的动态比特率控制器系统包括用于接收一个或多个输入参数的用户界面，比特率控制器和编码器。 比特率控制器调节输出比特流的比特率。 比特率控制器包括用于确定比特估计和量化参数的多个比特率模块，以及基于所接收的输入参数和帧速率来计算收敛周期的控制模块。 控制模块基于收敛周期选择比特率模块，并且编码器使用由比特率模块确定的量化参数来生成输出比特流。

公开(公告)号：US20110140748A1

公开(公告)日：2011-06-16

申请号：US12969220

申请日：2010-12-15

Applicant: Prateek Sikka ,  Rajesh Chopra ,  Manoj Yadav

Inventor： Prateek Sikka ,  Rajesh Chopra ,  Manoj Yadav

IPC: H03L7/06

CPC classification number: H03K5/135 ,  G06F17/5045

Abstract: The present disclosure provides an emulator mapping process on a system-on-a-chip (SoC) for debugging. The implementation reduces manual intervention and makes the emulation mapping process very generic and technology independent and hence it reduces overall project cycle time. In the present disclosure, the SoCs containing analog delay locked loops are made suitable for emulation by configuring analog delay locked loop module in parallel with a synthesizable delay logic module. Further, selection logic is provided to select any one of the module at a time.

Abstract translation: 本公开提供了用于调试的片上系统（SoC）上的仿真器映射过程。 该实现减少了手动干预，并使仿真映射过程非常通用和独立于技术，从而减少了整个项目周期的时间。 在本公开中，通过与可合成的延迟逻辑模块并联配置模拟延迟锁定环模块，包含模拟延迟锁定环路的SoC适于仿真。 此外，提供选择逻辑以一次选择模块中的任何一个。

公开(公告)号：US07944241B1

公开(公告)日：2011-05-17

申请号：US12697024

申请日：2010-01-29

Applicant: Vivek Mohan Sharma ,  Navneet Gupta

Inventor： Vivek Mohan Sharma ,  Navneet Gupta

IPC: H03K17/76 ,  G06F1/04

CPC classification number: G06F1/10

Abstract: A circuit for glitchless switching between asynchronous clocks includes a select circuit and enable circuits. The select circuit receives a selection signal for selecting one of the clock input signals and to generate enabling signals for activating the corresponding enable circuits on the basis of the current output signal. The feedback logic in the circuit ensures that at any given instance only one of the clock input signals is outputted so as to avoid the formation of glitches. The circuit can be applied to switches between any number of asynchronous clocks.

Abstract translation: 用于异步时钟之间无间断切换的电路包括选择电路和使能电路。 选择电路接收用于选择时钟输入信号之一的选择信号，并且基于当前输出信号产生用于激活相应的使能电路的使能信号。 电路中的反馈逻辑确保在任何给定的情况下，仅输出一个时钟输入信号以避免形成毛刺。 该电路可以应用于任意数量的异步时钟之间的切换。

公开(公告)号：US07902885B2

公开(公告)日：2011-03-08

申请号：US12006091

申请日：2007-12-28

Applicant: Vijender Singh Chauhan ,  Kallol Chatterjee ,  Paras Garg

Inventor： Vijender Singh Chauhan ,  Kallol Chatterjee ,  Paras Garg

IPC: H03B19/00

CPC classification number: H03K19/00384 ,  H03K19/018521

Abstract: The disclosure relates a compensated output buffer circuit providing an improved slew rate control and a method for minimizing the variations in the current slew rate of the buffer over process, voltage and temperature (PVT) conditions. The output buffer circuit includes a split-gate compensated driver and a slew rate control circuit. Accordingly, a desired slew rate can be maintained with fewer variations over wide range of variations in PVT conditions.

Abstract translation: 本公开涉及提供改进的转换速率控制的补偿输出缓冲电路和用于最小化缓冲器在过程，电压和温度（PVT）条件下的电流转换速率的变化的方法。 输出缓冲电路包括分闸门补偿驱动器和转换速率控制电路。 因此，可以在PVT条件的宽泛变化范围内以较少的变化来维持期望的转换速率。

公开(公告)号：US20110004647A1

公开(公告)日：2011-01-06

申请号：US12565596

申请日：2009-09-23

Applicant: Rakhel Kumar PARIDA ,  Ankur BAL ,  Anupam Jain

Inventor： Rakhel Kumar PARIDA ,  Ankur BAL ,  Anupam Jain

IPC: G06F17/17 ,  H03K5/00

CPC classification number: H03H17/0664 ,  H03H17/0282 ,  H03H17/0657 ,  H03H17/0671

Abstract: An offset free sinc interpolating filter includes differentiators operating at a first sampling frequency, integrators operating at a second sampling frequency and one or more coefficient multipliers. The coefficient multipliers multiply a received value with a constant coefficient value to generate an output value. The differentiators, integrators and coefficient multipliers can be operatively coupled to each other, either directly or through other components such as adders and delay elements, or by a combination of the two. In operation, an input signal is provided to the sinc interpolating filter at the first sampling frequency. The input signal is processed by the differentiators, integrators and coefficient multipliers to generate an output signal at the second sampling frequency. Once the output signal is generated, the integrators are reset before the next input cycle begins.

Abstract translation: 无偏移的正弦内插滤波器包括以第一采样频率工作的微分器，以第二采样频率工作的积分器和一个或多个系数乘法器。 系数乘法器将接收到的值与常数系数值相乘以产生输出值。 微分器，积分器和系数乘法器可以直接地或通过其他部件（例如加法器和延迟元件）或两者的组合来可操作地耦合。 在操作中，输入信号以第一采样频率提供给正弦内插滤波器。 输入信号由微分器，积分器和系数乘法器处理，以产生第二采样频率的输出信号。 产生输出信号后，积分器在下一个输入周期开始之前被复位。

公开(公告)号：US07808288B2

公开(公告)日：2010-10-05

申请号：US12006080

申请日：2007-12-28

Applicant: Kallol Chatterjee

Inventor： Kallol Chatterjee

IPC: H03L7/06

CPC classification number: H03L7/099 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1265 ,  H03B5/1293 ,  H03B2200/005 ,  H03L7/087 ,  H03L7/10

Abstract: Circuits and methods for an automatic coarse tuning in a phase locked loop (PLL) include observing a variation in a control voltage to disable a fine loop and to enable a coarse loop as the control voltage departs from a specified range. The circuit includes the fine loop, the coarse loop, and a control circuit. The fine loop includes a phase frequency detector (PFD), a charge pump, a loop filter, a VCO and a divider. The coarse loop includes a frequency detector, an up counter, a down counter, and an LC VCO. The control circuit includes a bandgap module, a comparator and other circuits such as a lock detect circuit. The control circuit is used to switch between the coarse loop and the fine loop.

Abstract translation: 用于锁相环（PLL）中的自动粗调的电路和方法包括观察控制电压的变化以禁用精细环路，并且当控制电压偏离指定范围时使能粗环路。 该电路包括微调环路，粗环路和控制电路。 精密回路包括相位频率检测器（PFD），电荷泵，环路滤波器，VCO和分频器。 粗调回路包括频率检测器，向上计数器，向下计数器和LC VCO。 控制电路包括带隙模块，比较器和诸如锁定检测电路的其它电路。 控制电路用于在粗环和微环之间切换。

公开(公告)号：US20100172199A1

公开(公告)日：2010-07-08

申请号：US12616696

申请日：2009-11-11

Applicant: Anand Kumar Mishra ,  Harsh Rawat

Inventor： Anand Kumar Mishra ,  Harsh Rawat

IPC: G11C7/02

CPC classification number: G11C7/18 ,  G11C7/02 ,  G11C7/065

Abstract: A balanced differential amplifier sense amplifier senses the voltage level in a selected single bit line memory cell. The output of the selected single bit-line memory cell is connected to one input of the balanced differential sense amplifier while the other input receives a reference voltage provided by a corresponding single bit-line memory cell from a complementary memory bank. A supporting voltage is added-to/subtracted-from the reference voltage by providing a “bump” or “dip” mechanism or by utilizing a charge-sharing structure, in order to compensate for the variation in the sensed bit-line voltage over the duration of the sensing interval as well as for the disparity in voltage level from cell to cell.

Abstract translation: 平衡差分放大器读出放大器检测所选单位线存储单元中的电压电平。 所选择的单位线存储单元的输出连接到平衡差分读出放大器的一个输入端，而另一输入端从互补存储体接收由相应的单位线存储单元提供的参考电压。 通过提供“凸起”或“倾斜”机制或通过利用电荷共享结构，从参考电压加入/减去支持电压，以便补偿所检测到的位线电压的变化 感测间隔的持续时间以及从细胞到细胞的电压水平的差异。