公开(公告)号：US20250037980A1

公开(公告)日：2025-01-30

申请号：US18359772

申请日：2023-07-26

Applicant: Applied Materials, Inc.

Inventor： Rupankar Choudhury ,  Sanjay G. Kamath ,  Juan Carlos Rocha-Alvarez ,  Sridhar Bachu ,  Mukesh Singh Dhami ,  Dan-il Yoon

IPC: H01J37/32 ,  C23C16/44 ,  C23C16/455

Abstract: A processing chamber and port adaptor are provided. Processing chambers include a chamber body having a lid coupled to the first end of the chamber body, a gas ring adjacent the first end of the chamber body, and a substrate support, where a processing region is defined between the substrate support and the lid. The processing chamber includes a port adapter coupled to the second end of the chamber body. The port adapter includes a body defining a plurality of apertures in fluid communication with the processing region, where each of the apertures are spaced apart along the body such that a distance between adjacent apertures is within about 20% of an average aperture spacing distance, an individually controllable valve fluidly coupled to one or more of the plurality of apertures, and an exhaust system in fluid communication with a system foreline and the plurality of apertures.

公开(公告)号：US20250037978A1

公开(公告)日：2025-01-30

申请号：US18225454

申请日：2023-07-24

Applicant: Applied Materials, Inc.

Inventor： Sanjeev Baluja ,  Chaowei Wang ,  Kevin Griffin ,  Kenneth Brian Doering ,  Hanhong Chen ,  Joseph AuBuchon

IPC: H01J37/32 ,  H01L21/67

Abstract: Gas distribution assemblies for semiconductor devices are described. The gas distribution assemblies include a backplate, a faceplate, a counterbored hole, and at least one orifice. The at least one orifice includes, for example, at least one straight orifice, or at least two angled orifices. Some embodiments of the gas distribution assemblies provide for reduced plasma damage in a processing chamber. Some embodiments of the gas distribution assemblies provide for reduced jetting on a substrate in a processing chamber. Methods of reducing plasma damage in gas distribution assemblies are also described.

公开(公告)号：US12211736B2

公开(公告)日：2025-01-28

申请号：US17515773

申请日：2021-11-01

Applicant: Applied Materials, Inc.

Inventor： Hurshvardhan Srivastava ,  Keith T. Wong

IPC: H01L21/762 ,  C23C16/40 ,  H01L21/02 ,  H01J37/32

Abstract: Exemplary deposition methods may include introducing a vapor of a metal alkoxide into a processing volume of a semiconductor processing chamber. A substrate defining a trench may be housed in the processing volume. The methods may include condensing the vapor into a liquid metal alkoxide within the trench on the substrate. The methods may include forming a plasma external to the processing volume of the semiconductor processing chamber. The methods may include introducing plasma-generated species into the processing volume. The methods may include exposing the liquid metal alkoxide in the trench to the plasma-generated species. The methods may also include forming a metal oxide film in the trench through a reaction between the liquid metal alkoxide and the plasma-generated species.

公开(公告)号：US12211677B2

公开(公告)日：2025-01-28

申请号：US17382332

申请日：2021-07-21

Applicant: Applied Materials, Inc.

Inventor： Vladimir Nagorny ,  Rene George

IPC: H01J37/32 ,  G06N20/00

Abstract: A system and method including a processing device. The processing device receives data including one or more plasma exposure durations of a plasma process. The plasma exposure duration are associated with a set of controlled elements. The processing device causes a each set of controlled elements to switch between a first mode of operation and a second mode of operation. Each set of controlled elements expose appropriate portion of a substrate to the plasma related fluxes. The first set of controlled elements process the substrate at an increased rate while operating in the first mode of operation relative to the second mode of operation. The processing device causes each set of controlled elements to operate in the first mode of operation for the appropriate time duration based on the received plasma exposure duration data.

公开(公告)号：US12209663B2

公开(公告)日：2025-01-28

申请号：US18215604

申请日：2023-06-28

Applicant: Applied Materials, Inc.

Inventor： Yao-Hung Yang ,  Chih-Yang Chang ,  Sam Hyungsam Kim

IPC: F16J15/06 ,  F16J15/02 ,  F16J15/10

Abstract: A sealing member includes a monolithic body including a first portion adjoining a second portion. The first portion forms part of a circle. The second portion includes first and second lobes. Each lobe adjoins the first portion with a concave surface. In one example, each lobe includes a rounded tip, and a convex surface extends from one rounded tip to the other rounded tip.

公开(公告)号：US20250029850A1

公开(公告)日：2025-01-23

申请号：US18224996

申请日：2023-07-21

Applicant: Applied Materials, Inc.

Inventor： Kim Ramkumar VELLORE ,  Tetsuya ISHIKAWA ,  Ala MORADIAN

IPC: H01L21/67 ,  H01L21/66 ,  H01L21/687

Abstract: The present disclosure relates to methods of analyzing uniformity for substrate processing, and related apparatus and systems, for semiconductor manufacturing. In one or more embodiments, a non-uniformity is indicated, and the non-uniformity is a temperature non-uniformity and/or a physical non-uniformity. In one or more embodiments, a signal profile is accepted or rejected. In one or more embodiments, a method of analyzing uniformity for substrate processing applicable for semiconductor manufacturing includes heating an internal volume of a processing chamber using a target value. The method includes rotating a substrate support, and scanning, while rotating the substrate support, a sensor across one or more sections to take a plurality of readings. The method includes generating a signal profile including the plurality of readings, and analyzing the signal profile by comparing the signal profile to a range.

公开(公告)号：US20250029849A1

公开(公告)日：2025-01-23

申请号：US18223184

申请日：2023-07-18

Applicant: Applied Materials, Inc.

Inventor： Anish Janakiraman ,  Mayur Govind Kulkarni ,  Deenesh Padhi

IPC: H01L21/67 ,  H01L21/687

Abstract: Exemplary semiconductor processing chambers may include a chamber body. The chambers may include a substrate support within the chamber body. The substrate support may define a substrate support surface. The chambers may include a faceplate supported atop the chamber body. The substrate support and a bottom surface of the faceplate may at least partially define a processing region. The bottom surface of the faceplate may define an annular protrusion that is directly above at least a portion of a radially outer 10% of the substrate support surface and an annular groove that is positioned radially outward of the annular protrusion. At least a portion of the annular groove may extend radially outward beyond the substrate support surface. The faceplate may define apertures through the faceplate. A first subset of the apertures may extend through the annular protrusion and a second subset of the apertures may extend through the annular groove.

公开(公告)号：US20250029816A1

公开(公告)日：2025-01-23

申请号：US18773859

申请日：2024-07-16

Applicant: Applied Materials, Inc.

Inventor： Douglas Long ,  Vinod Kumar Konda Purathe ,  Dien-Yeh Wu ,  Jallepally Ravi ,  Hideaki Goto ,  Manjunatha Koppa ,  Hiroyuki Takahama ,  Shih Yao Hsu ,  Sandesh Yadamane Dharmaiah

IPC: H01J37/32 ,  C23C16/455

Abstract: Gas distribution assemblies for a semiconductor manufacturing processing chamber comprising a first showerhead with a first flange and a second showerhead with a second flange. A first two-piece RF isolator comprises a first inner RF isolator spaced from a first outer RF isolator. The first inner RF isolator spaced from the first flange of the first showerhead to create a first flow path. A second two-piece RF isolator comprises a second inner RF isolator spaced from a second outer RF isolator. The second RF isolator spaced from the second flange of the second showerhead to create a second flow path. Processing chambers incorporating the gas distribution assemblies, and processing methods using the gas distribution assemblies are also described.

公开(公告)号：US20250027195A1

公开(公告)日：2025-01-23

申请号：US18223199

申请日：2023-07-18

Applicant: Applied Materials, Inc.

Inventor： Yogesh Tomar ,  Nikshep Patil ,  Kirubanandan Shanmugam Naina ,  Hanish Kumar Panavalappil Kumarankutty ,  Gayatri Natu ,  Mahesh Chelvaraj Arcot ,  Senthil Kumar Nattamai Subramanian ,  Hari Venkatesh Rajendran ,  Michael Rice ,  Christopher Laurent Beaudry

IPC: C23C16/455 ,  C23C16/44 ,  C23C16/52

Abstract: A method includes performing an atomic layer deposition (ALD) process with respect to a plurality of target elements to coat interiors of the plurality of target elements with a protective coating. Performing the ALD process includes alternating delivery of a first precursor inside the plurality of target elements for a first duration to form an adsorption layer on the interiors of the plurality of target elements, alternating purging of the first precursor from the plurality of target elements for a second duration, and alternating delivery of a second precursor inside the plurality of target elements for a third duration to cause the second precursor to react with the adsorption layer and form a target layer on the interiors of the plurality of target elements.

公开(公告)号：US12207458B2

公开(公告)日：2025-01-21

申请号：US17680993

申请日：2022-02-25

Applicant: Applied Materials, Inc.

Inventor： Fredrick David Fishburn

IPC: H10B12/00

Abstract: Methods for forming 3D DRAM leverage L-pad formations to increase memory density. Methods may include etching a substrate to form two Si walls oriented parallel to each other and forming a space therebetween, depositing a plurality of alternating Si layers and SiGe layers using epitaxial growth processes to form horizontal deposition layers on the space between the two Si walls and vertical deposition layers on sidewalls of the two Si walls, depositing a CMP stop layer on the substrate, planarizing the substrate to the CMP stop layer, removing a portion of a top of the two Si walls and forming an L-pad formation, deep etching a pattern of holes into the space between the two Si walls in horizontal portions of the plurality of alternating Si layers and SiGe layers, and forming vertical wordline structures from the pattern of holes in the horizontal portions.