公开(公告)号：US20130252559A1

公开(公告)日：2013-09-26

申请号：US13599413

申请日：2012-08-30

申请人： Jun DEGUCHI ,  Shouhei Kousai ,  Yousuke Hagiwara ,  Masamichi Suzuki ,  Atsuhiro Kinoshita ,  Takao Marukame

发明人： Jun DEGUCHI ,  Shouhei Kousai ,  Yousuke Hagiwara ,  Masamichi Suzuki ,  Atsuhiro Kinoshita ,  Takao Marukame

IPC分类号： H03M1/66

CPC分类号： H03M1/66 ,  H03M1/1061 ,  H03M1/745

摘要： In general, according to one embodiment, a DA converter configured to convert a digital signal comprising n (n>1) bits to an analog current to output the analog current from an output terminal, includes n voltage-current converters. Each of them corresponds to each bit of the digital signal and is configured to generate a current depending on the corresponding bit. A k-th (k is an integer of 0 to n−1) voltage-current converter includes a first transistor whose threshold voltage is adjustable. The first transistor includes a semiconductor substrate, a first diffusion region, a second diffusion region, an insulating film, a charge accumulating film, and a gate.

摘要翻译： 通常，根据一个实施例，配置成将包括n（n> 1）位的数字信号转换为模拟电流以从输出端输出模拟电流的DA转换器包括n个电压 - 电流转换器。 它们中的每一个对应于数字信号的每个位，并且被配置为根据相应的位产生电流。 第k（k是0到n-1的整数）电压 - 电流转换器包括阈值电压可调的第一晶体管。 第一晶体管包括半导体衬底，第一扩散区，第二扩散区，绝缘膜，电荷累积膜和栅极。

公开(公告)号：US08476690B2

公开(公告)日：2013-07-02

申请号：US13223331

申请日：2011-09-01

申请人： Daisuke Hagishima ,  Atsuhiro Kinoshita

发明人： Daisuke Hagishima ,  Atsuhiro Kinoshita

IPC分类号： G11C16/04 ,  H01L29/788

CPC分类号： H01L29/788 ,  G11C16/0416 ,  G11C16/0466 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11534 ,  H01L27/11807

摘要： A nonvolatile programmable logic switch according to an embodiment includes: a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type; a memory cell transistor including a first insulating film formed on the first semiconductor region, a charge storage film formed on the first insulating film, a second insulating film formed on the charge storage film, and a control gate formed on the second insulating film; a pass transistor including a third insulating film formed on the second semiconductor region, and a gate electrode formed on the third insulating film and electrically connected to the first drain region; a first electrode applying a substrate bias to the first semiconductor region, the first electrode being formed in the first semiconductor region; and a second electrode applying a substrate bias to the second semiconductor region, the second electrode being formed in the second semiconductor region.

摘要翻译： 根据实施例的非易失性可编程逻辑开关包括：第一导电类型的第一半导体区域和第二导电类型的第二半导体区域; 存储单元晶体管，包括形成在第一半导体区域上的第一绝缘膜，形成在第一绝缘膜上的电荷存储膜，形成在电荷存储膜上的第二绝缘膜，以及形成在第二绝缘膜上的控制栅; 包括形成在第二半导体区域上的第三绝缘膜的通过晶体管和形成在第三绝缘膜上并电连接到第一漏极区的栅电极; 将第一电极施加到所述第一半导体区域的衬底偏压，所述第一电极形成在所述第一半导体区域中; 以及向所述第二半导体区域施加衬底偏压的第二电极，所述第二电极形成在所述第二半导体区域中。

公开(公告)号：US08450208B2

公开(公告)日：2013-05-28

申请号：US13081629

申请日：2011-04-07

申请人： Yoshifumi Nishi ,  Atsuhiro Kinoshita ,  Hirotaka Nishino ,  Masamichi Suzuki

发明人： Yoshifumi Nishi ,  Atsuhiro Kinoshita ,  Hirotaka Nishino ,  Masamichi Suzuki

IPC分类号： H01L21/283

CPC分类号： H01L21/28518 ,  H01L29/1608 ,  H01L29/41708 ,  H01L29/456 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/6609 ,  H01L29/66272 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66712 ,  H01L29/732 ,  H01L29/7833 ,  H01L29/861

摘要： In a semiconductor device manufacturing method according to an exemplary embodiment, a sulfur-containing film containing sulfur is deposited on an n-type semiconductor, a first metal film containing a first metal is deposited on the sulfur-containing film, a heat treatment is performed to form a metal semiconductor compound film by reacting the n-type semiconductor and the sulfur-containing film, and to introduce sulfur to an interface between the n-type semiconductor and the metal semiconductor compound film being formed.

摘要翻译： 在根据示例性实施例的半导体器件制造方法中，在n型半导体上沉积含硫的含硫膜，在含硫膜上沉积含有第一金属的第一金属膜，进行热处理 通过使n型半导体和含硫膜反应形成金属半导体化合物膜，并将硫引入到正在形成的n型半导体与金属半导体化合物膜之间的界面上。

公开(公告)号：US20130042060A1

公开(公告)日：2013-02-14

申请号：US13569605

申请日：2012-08-08

申请人： Takao MARUKAME ,  Atsuhiro Kinoshita ,  Kosuke Tatsumura

发明人： Takao MARUKAME ,  Atsuhiro Kinoshita ,  Kosuke Tatsumura

IPC分类号： G06F12/00

CPC分类号： G06F17/30982 ,  G06F12/0246 ,  G06F17/30097 ,  G06F17/3012 ,  G06F2212/7201

摘要： According to one embodiment, a memory system including a key-value store containing key-value data as a pair of a key and a value corresponding to the key, includes an interface, a memory block, an address acquisition circuit and a controller. The interface receives a data write/read request or a request based on the key-value store. The memory block has a data area for storing data and a metadata table containing the key-value data. The address acquisition circuit acquires an address in response to input of the key. The controller executes the data write/read request for the memory block, and outputs the address acquired to the memory block and executes the request based on the key-value store. The controller outputs the value corresponding to the key via the interface.

公开(公告)号：US20120218802A1

公开(公告)日：2012-08-30

申请号：US13403398

申请日：2012-02-23

申请人： Takao MARUKAME ,  Tomoaki INOKUCHI ,  Hideyuki SUGIYAMA ,  Mizue ISHIKAWA ,  Yoshiaki SAITO ,  Atsuhiro KINOSHITA ,  Kosuke TATSUMURA

发明人： Takao MARUKAME ,  Tomoaki INOKUCHI ,  Hideyuki SUGIYAMA ,  Mizue ISHIKAWA ,  Yoshiaki SAITO ,  Atsuhiro KINOSHITA ,  Kosuke TATSUMURA

IPC分类号： G11C15/02

CPC分类号： G11C15/02 ,  G11C11/161 ,  G11C15/046 ,  H01L27/228

摘要： One embodiment provides a content addressable memory, including: a pair of spin MOSFETs including: a first spin MOSFET whose magnetization state is set in accordance with stored data; and a second spin MOSFET whose magnetization state is set in accordance with the stored data, the second spin MOSFET being connected in parallel with the first spin MOSFET; a first wiring configured to apply a gate voltage so that any one of the first spin MOSFET and the second spin MOSFET becomes electrically conductive in accordance with search data; and a second wiring configured to apply a current to both of the first spin MOSFET and the second spin MOSFET.

摘要翻译： 一个实施例提供一种内容可寻址存储器，包括：一对自旋MOSFET，其包括：第一自旋MOSFET，其磁化状态根据存储的数据设置; 以及第二自旋MOSFET，其磁化状态根据存储的数据设定，第二自旋MOSFET与第一自旋MOSFET并联连接; 第一布线，被配置为施加栅极电压，使得第一自旋MOSFET和第二自旋MOSFET中的任何一个根据搜索数据变为导电; 以及配置为向第一自旋MOSFET和第二自旋MOSFET两者施加电流的第二布线。

公开(公告)号：US20120068241A1

公开(公告)日：2012-03-22

申请号：US13236734

申请日：2011-09-20

申请人： Kiwamu SAKUMA ,  Atsuhiro KINOSHITA

发明人： Kiwamu SAKUMA ,  Atsuhiro KINOSHITA

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L27/11578 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11565 ,  H01L29/785 ,  H01L29/792

摘要： According to one embodiment, a memory device includes first and second fin type stacked structures each includes first to i-th memory strings (i is a natural number except 1) that are stacked in a first direction, the first and second fin type stacked structures which extend in a second direction and which are adjacent in a third direction, a first portion connected to one end in the second direction of the first fin type stacked structure, a width in the third direction of the first portion being greater than a width in the third direction of the first fin type stacked structure, and a second portion connected to one end in the second direction of the second fin type stacked structure, a width in the third direction of the second portion being greater than a width in the third direction of the second fin type stacked structure.

摘要翻译： 根据一个实施例，存储器件包括第一和第二鳍式堆叠结构，每个第一和第二鳍式堆叠结构每个包括沿第一方向堆叠的第一至第i存储器串（i是除1之外的自然数），第一和第二鳍式堆叠结构 其在第二方向上延伸并且在第三方向上相邻，第一部分连接到第一鳍式堆叠结构的第二方向上的一端，第一部分的第三方向上的宽度大于第一方向上的宽度 第一鳍式堆叠结构的第三方向和与第二鳍式堆叠结构的第二方向的一端连接的第二部分，第二部分的第三方向上的宽度大于第三方向上的宽度 的第二鳍式堆叠结构。

公开(公告)号：US20110254062A1

公开(公告)日：2011-10-20

申请号：US13042590

申请日：2011-03-08

申请人： Tatsuo Shimizu ,  Atsuhiro Kinoshita ,  Hirotaka Nishino

发明人： Tatsuo Shimizu ,  Atsuhiro Kinoshita ,  Hirotaka Nishino

IPC分类号： H01L29/772 ,  H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823857 ,  H01L21/28185 ,  H01L21/3115 ,  H01L21/31155 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A field effect transistor which can operate at a low threshold value includes: an n-type semiconductor region; a source region and a drain region separately formed in the n-type semiconductor region; a first insulating film formed in the semiconductor region between the source region and the drain region and containing silicon and oxygen; a second insulating film formed on the first insulating film and containing at least one material selected from Hf, Zr, and Ti and oxygen; and a gate electrode formed on the second insulating film. Ge is doped in an interface region including an interface between the first insulating film and the second insulating film, and an area density of the Ge has a peak on a first insulating film side in the interface region.

摘要翻译： 可以以低阈值工作的场效应晶体管包括：n型半导体区域; 分别形成在所述n型半导体区域中的源极区域和漏极区域; 形成在源极区域和漏极区域之间并且含有硅和氧的半导体区域中的第一绝缘膜; 形成在所述第一绝缘膜上并且包含选自Hf，Zr和Ti中的至少一种材料和氧的第二绝缘膜; 以及形成在所述第二绝缘膜上的栅电极。 Ge掺杂在包括第一绝缘膜和第二绝缘膜之间的界面的界面区域中，Ge的面密度在界面区域的第一绝缘膜侧具有峰值。

公开(公告)号：US20100109099A1

公开(公告)日：2010-05-06

申请号：US12609805

申请日：2009-10-30

申请人： Yoshifumi NISHI ,  Atsuhiro Kinoshita

发明人： Yoshifumi NISHI ,  Atsuhiro Kinoshita

IPC分类号： H01L29/78 ,  H01L29/417 ,  H01L21/22 ,  H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/265 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/28537 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/095 ,  H01L29/66507 ,  H01L29/7833

摘要： A semiconductor device including a semiconductor substrate, an interface layer formed on the semiconductor substrate including at least 1×1020 atoms/cm3 of S (Sulfur), a metal-semiconductor compound layer formed on the interface layer, the metal-semiconductor compound layer including at least 1×1020 atoms/cm3 of S in the its whole depth, and a metal electrode formed on the metal-semiconductor compound layer.

摘要翻译： 一种半导体器件，包括半导体衬底，形成在所述半导体衬底上的界面层，所述界面层至少包含1×1020原子/ cm3的S（硫），在所述界面层上形成的金属 - 半导体化合物层，所述金属 - 半导体化合物层包括 在整个深度上至少为1×1020原子/ cm3的S，以及形成在金属 - 半导体化合物层上的金属电极。

公开(公告)号：US07479674B2

公开(公告)日：2009-01-20

申请号：US12034822

申请日：2008-02-21

申请人： Yukio Nakabayashi ,  Kazumi Nishinohara ,  Atsuhiro Kinoshita ,  Junji Koga

发明人： Yukio Nakabayashi ,  Kazumi Nishinohara ,  Atsuhiro Kinoshita ,  Junji Koga

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L29/66643 ,  H01L29/66795 ,  H01L29/7839 ,  H01L29/78621

摘要： An field effect transistor includes a first semiconductor region, a gate electrode insulatively disposed over the first semiconductor region, source and drain electrodes between which the first semiconductor region is sandwiched, and second semiconductor regions each formed between the first semiconductor region and one of the source and drain electrodes, and having impurity concentration higher than that of the first semiconductor region, the source electrode being offset to the gate electrode in a direction in which the source electrode and the drain electrode are separated from each other with respect to a channel direction, and one of the second semiconductor regions having a thickness not more than a thickness with which the one of second semiconductor regions is completely depleted in the channel direction being in thermal equilibrium with the source electrode therewith.

摘要翻译： 场效应晶体管包括第一半导体区域，绝缘地设置在第一半导体区域上的栅极电极，夹在第一半导体区域之间的源极和漏极电极以及形成在第一半导体区域和源极之一之间的第二半导体区域 和漏电极，其杂质浓度高于第一半导体区域，源电极在源电极和漏电极相对于沟道方向彼此分离的方向上偏移到栅电极， 并且所述第二半导体区域中的一个具有不大于所述第二半导体区域中的所述第二半导体区域在所述沟道方向上完全耗尽的厚度的厚度与所述源极电极处于热平衡。

公开(公告)号：US20080140344A1

公开(公告)日：2008-06-12

申请号：US12015147

申请日：2008-01-16

申请人： Hiroshi Watanabe ,  Atsuhiro Kinoshita

发明人： Hiroshi Watanabe ,  Atsuhiro Kinoshita

IPC分类号： G04F10/00

CPC分类号： G04F10/10

摘要： A system LSI including a semiconductor chip which receives power from a power supply, and an electronic timer which measures a time from an interruption of power supplying to the semiconductor chip to a resumption of power supplying to the semiconductor chip.

摘要翻译： 包括从电源接收电力的半导体芯片的系统LSI和测量从半导体芯片的供电中断恢复向半导体芯片供电的时间的电子计时器。