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    Systems and methods for digital data transmission rate control
    31.
    发明授权
    Systems and methods for digital data transmission rate control 有权
    数字数据传输速率控制的系统和方法

    公开(公告)号：US08611215B2

    公开(公告)日：2013-12-17

    申请号：US13240017

    申请日：2011-09-22

    Applicant: Behnam Katibian ,  George A. Wiley ,  Brian Steele

    Inventor： Behnam Katibian ,  George A. Wiley ,  Brian Steele

    IPC: H04J1/16

    CPC classification number: H04L47/10 ,  H04L47/19 ,  H04L47/365 ,  H04N21/238 ,  H04N21/23805 ,  H04N21/44209 ,  H04N21/6377 ,  H04N21/658 ,  H04N21/6587

    Abstract: The present invention provides systems and methods for adaptive digital data transmission rate control. A digital data transmission system for adaptively transferring packets over a transmission link includes a client device having a bandwidth control module and a host device coupled to the client device over the transmission link. The host device includes one or more bandwidth control registers and a packet builder. The bandwidth control module determines a packet speed and/or size for packets transmitted from the host device to the client device over the transmission link. The bandwidth control registers store the requested packet size and/or rate. The packet builder accesses these registers when transmitting packets to determine the requested packet size and/or rate.

    Abstract translation: 本发明提供了用于自适应数字数据传输速率控制的系统和方法。 用于通过传输链路自适应地传送分组的数字数据传输系统包括具有带宽控制模块的客户端设备和通过传输链路耦合到客户端设备的主机设备。 主机设备包括一个或多个带宽控制寄存器和数据包生成器。 带宽控制模块通过传输链路确定从主机设备向客户端设备发送的分组的分组速度和/或大小。 带宽控制寄存器存储所请求的分组大小和/或速率。 分组构建器在发送分组时访问这些寄存器以确定所请求的分组大小和/或速率。

    METHODS AND SYSTEMS FOR OPERATING A COMPUTER VIA A LOW POWER ADJUNCT PROCESSOR
    32.
    发明申请
    METHODS AND SYSTEMS FOR OPERATING A COMPUTER VIA A LOW POWER ADJUNCT PROCESSOR 有权
    用于通过低功率ADJUNCT处理器操作计算机的方法和系统

    公开(公告)号：US20110055434A1

    公开(公告)日：2011-03-03

    申请号：US12551530

    申请日：2009-08-31

    Applicant: James PYERS ,  George WILEY ,  James J. WILLKIE ,  Brian STEELE ,  Apul NAHATA ,  Karthik Raj KALIANNAN

    Inventor： James PYERS ,  George WILEY ,  James J. WILLKIE ,  Brian STEELE ,  Apul NAHATA ,  Karthik Raj KALIANNAN

    IPC: G06F3/00 ,  G06F12/00 ,  G06F13/00 ,  G06F3/048 ,  G06F15/16 ,  G06F13/20

    CPC classification number: G06F1/3203 ,  G06F1/3293 ,  Y02D10/122

    Abstract: A computing device includes a low power auxiliary processor, such as a processor on a wireless card or sub-system, which is able to takeover processing in place of the computing device's central processing unit (CPU). Operating the computing device on the auxiliary processor draws less power from the computing device battery, enabling extended operation in an auxiliary processor mode. When in this mode, the auxiliary processor controls peripherals and provides the system functionality while the CPU is deactivated, such as in “off,” “standby” or “sleep” modes. In the auxiliary processor mode, the computing device can accomplish useful tasks, such as sending/receiving electronic mail, displaying electronic documents and accessing a network while drawing minimal power from the battery. Transitions between the normal operating mode and auxiliary processor mode may be transparent to users. Such a computer may display instant on, always on and always connected operating features.

    Abstract translation: 计算设备包括能够接管处理代替计算设备的中央处理单元（CPU）的低功率辅助处理器，诸如无线卡或子系统上的处理器。 在辅助处理器上操作计算设备从计算设备电池吸取更少的电力，从而能够在辅助处理器模式下进行扩展操作。 在此模式下，辅助处理器控制外设，并在CPU被关闭时提供系统功能，例如处于“关闭”，“待机”或“睡眠”模式。 在辅助处理器模式中，计算设备可以完成有用的任务，例如发送/接收电子邮件，显示电子文档和访问网络，同时从电池中抽取最小功率。 正常操作模式和辅助处理器模式之间的转换可能对用户来说是透明的。 这样的计算机可以立即显示，始终处于和始终连接的操作特征。

    Double data rate serial encoder
    33.
    发明申请
    Double data rate serial encoder 有权
    双数据率串行编码器

    公开(公告)号：US20060179384A1

    公开(公告)日：2006-08-10

    申请号：US11285397

    申请日：2005-11-23

    Applicant: George Wiley ,  Brian Steele ,  Curtis Musfeldt

    Inventor： George Wiley ,  Brian Steele ,  Curtis Musfeldt

    IPC: G01R31/28 ,  G06F11/00

    CPC classification number: H04J3/047 ,  H04L25/0264 ,  H04L25/028 ,  H04L25/0292

    Abstract: A double data rate serial encoder is provided. The serial encoder comprises a mux having a plurality of inputs, a plurality of latches coupled to the inputs of the mux, an enabler to enable the latches to update their data inputs, and a counter to select one of the plurality of inputs of the mux for output. In another aspect, the mux provides a glitch-less output during input transitions. The mux includes an output selection algorithm optimized based on a priori knowledge of an input selection sequence provided by the counter.

    Abstract translation: 提供双数据速率串行编码器。 串行编码器包括具有多个输入的多路复用器，耦合到多路复用器的输入的多个锁存器，使得锁存器能够更新其数据输入的启动器，以及用于选择多路复用器的多个输入之一的计数器 用于输出。 在另一方面，多路复用器在输入转换期间提供无毛刺输出。 多路复用器包括基于由计数器提供的输入选择序列的先验知识而优化的输出选择算法。

    High data rate interface
    37.
    发明申请
    High data rate interface 有权
    高数据速率接口

    公开(公告)号：US20050120079A1

    公开(公告)日：2005-06-02

    申请号：US10938354

    申请日：2004-09-10

    Applicant: Jon Anderson ,  Brian Steele ,  George Wiley ,  Shashank Shekhar

    Inventor： Jon Anderson ,  Brian Steele ,  George Wiley ,  Shashank Shekhar

    IPC: H04L12/28 ,  H04L12/56 ,  H04L29/06 ,  H04M1/725 ,  G06F15/16 ,  G06F13/00

    CPC classification number: H04L65/607 ,  H04L29/06027 ,  H04L69/14 ,  H04L69/18 ,  H04L69/22 ,  H04L69/24 ,  H04M1/72527 ,  Y02D50/30 ,  Y02D70/00 ,  Y02D70/122 ,  Y02D70/144 ,  Y02D70/26

    Abstract: A data Interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range “serial” type data link, which lends itself to implementation with miniature connectors and thin flexible cables which are especially useful in connecting display elements such as wearable micro-displays to portable computers and wireless communication devices.

    Abstract translation: 一种数据接口，用于通过连接在一起的分组结构通过通信路径在主机和客户端之间传送数字数据，以形成用于传送预先选择的一组数字控制和呈现数据的通信协议。 信号协议被配置为生成，发送和接收形成通信协议的分组的链路控制器使用，并且将数字数据形成为一个或多个类型的数据分组，其中至少一个驻留在主机设备中并耦合到 客户端通过通信路径。 该接口通过短距离“串行”类型数据链路提供了经济高效，低功耗，双向，高速的数据传输机制，可实现微型连接器和薄型柔性电缆，特别适用于 将可穿戴式微型显示器等显示元件连接到便携式计算机和无线通信装置。

    System for transferring digital data at a high rate between a host and a client over a communication path for presentation to a user
    38.
    发明授权
    System for transferring digital data at a high rate between a host and a client over a communication path for presentation to a user 有权
    用于通过通信路径在主机和客户端之间以高速率传送数字数据以呈现给用户的系统

    公开(公告)号：US08694663B2

    公开(公告)日：2014-04-08

    申请号：US12836891

    申请日：2010-07-15

    Applicant: Qiuzhen Zou ,  George Alan Wiley ,  Brian Steele

    Inventor： Qiuzhen Zou ,  George Alan Wiley ,  Brian Steele

    IPC: G06F13/00

    CPC classification number: H04L29/06 ,  G06F3/14 ,  G09G5/006 ,  G09G5/008 ,  G09G5/12 ,  G09G2370/10 ,  G09G2370/16 ,  H04L47/10 ,  H04L47/283 ,  H04L47/41 ,  H04L69/324

    Abstract: A data Interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range “serial” type data link, which lends itself to implementation with miniature connectors and thin flexible cables which are especially useful in connecting display elements such as wearable micro-displays to portable computers and wireless communication devices.

    Abstract translation: 一种数据接口，用于通过连接在一起的分组结构通过通信路径在主机和客户端之间传送数字数据，以形成用于传送预先选择的一组数字控制和呈现数据的通信协议。 信号协议被配置为生成，发送和接收形成通信协议的分组的链路控制器使用，并且将数字数据形成为一个或多个类型的数据分组，其中至少一个驻留在主机设备中并耦合到 客户端通过通信路径。 该接口通过短距离“串行”类型数据链路提供了经济高效，低功耗，双向，高速的数据传输机制，可实现微型连接器和薄型柔性电缆，特别适用于 将可穿戴式微型显示器等显示元件连接到便携式计算机和无线通信装置。

    ADJUSTING BIT-LINE DISCHARGE TIME IN MEMORY ARRAYS BASED ON CHARACTERIZED WORD-LINE DELAY AND GATE DELAY
    40.
    发明申请
    ADJUSTING BIT-LINE DISCHARGE TIME IN MEMORY ARRAYS BASED ON CHARACTERIZED WORD-LINE DELAY AND GATE DELAY 失效
    基于特征字长延迟和门延时调整存储器阵列中的位线放电时间

    公开(公告)号：US20140071775A1

    公开(公告)日：2014-03-13

    申请号：US13606342

    申请日：2012-09-07

    Applicant: Donald Albert Evans ,  Rasoju Veerabadra Chary ,  Richard John Stephani ,  Bijan Kumar Ghosh ,  Ronald Brian Steele

    Inventor： Donald Albert Evans ,  Rasoju Veerabadra Chary ,  Richard John Stephani ,  Bijan Kumar Ghosh ,  Ronald Brian Steele

    IPC: G11C7/22

    CPC classification number: G11C7/00 ,  G11C7/04 ,  G11C7/12 ,  G11C7/222 ,  G11C7/227 ,  G11C29/02 ,  G11C29/023 ,  G11C2029/1204

    Abstract: A memory tracking circuit controls discharge duration of a tracking bit-line based on (i) a signal received at the far end of a tracking row after a propagation delay and (ii) a signal applied to a transistor-based gate delay. The tracking circuit (i) extends the discharge duration when one or more of (a) the propagation delay and (b) the transistor-based gate delay is shorter than an uncontrolled discharge duration of the tracking bit-line, and (ii) does not extend the discharge duration otherwise. Based on the discharge duration, the tracking circuit activates a reset signal that resets a clock-pulse generator to switch the memory from an access operation to a recess state. Controlling the discharge duration, and consequently the reset signal, based on the propagation delay and the gate delay allows the clock-pulse generator to adjust access times to account for the memory array configuration and process, temperature, and voltage conditions.

    Abstract translation: 存储器跟踪电路基于（i）在传播延迟之后在跟踪行的远端接收的信号和（ii）施加到基于晶体管的门延迟的信号来控制跟踪位线的放电持续时间。 跟踪电路（i）在（a）传播延迟和（b）基于晶体管的栅极延迟短于跟踪位线的不受控制的放电持续时间的一个或多个时延长放电持续时间，并且（ii） 否则不延长放电持续时间。 基于放电持续时间，跟踪电路激活复位信号，其复位时钟脉冲发生器以将存储器从访问操作切换到凹陷状态。 基于传播延迟和门延迟来控制放电持续时间以及因此复位信号允许时钟脉冲发生器调整存取时间以解决存储器阵列配置和处理，温度和电压条件。

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