公开(公告)号：US07835706B2

公开(公告)日：2010-11-16

申请号：US11224391

申请日：2005-09-12

Applicant: David R. Welland ,  Ramkishore Ganti ,  CaiYi Wang

Inventor： David R. Welland ,  Ramkishore Ganti ,  CaiYi Wang

IPC: H04B1/40

CPC classification number: H04B1/403

Abstract: An RF transmitter (104) includes a shared local oscillator circuit (126), transmit path circuitry (120, 122, 124), a divider (134), and a lowpass filter (322). The shared local oscillator circuit (126) generates a shared LO signal (116). The transmit path circuitry (120, 122, 124) mixes a baseband signal (107) and an IF mixing signal (116) to provide an IF signal (112), and converts the IF signal (112) to an RF transmit signal (105) at a desired frequency using an RF mixing signal received at a mixing input thereof. The divider (134) divides the shared LO signal (116) to provide an unfiltered RF mixing signal. The lowpass filter (322) has an input for receiving the unfiltered RF mixing signal, and an output coupled to the mixing input of the transmit path circuitry (120, 122, 124) for providing the RF mixing signal.

Abstract translation: RF发射机（104）包括共享本地振荡器电路（126），发射路径电路（120,122,124），分频器（134）和低通滤波器（322）。 共享本地振荡器电路（126）产生共享LO信号（116）。 发射路径电路（120,122,124）混合基带信号（107）和IF混合信号（116）以提供IF信号（112），并将IF信号（112）转换成RF发射信号（105 ），使用在其混合输入端接收的RF混频信号。 分频器（134）划分共享LO信号（116）以提供未滤波的RF混频信号。 低通滤波器（322）具有用于接收未滤波的RF混频信号的输入端和耦合到发射路径电路（120,122,124）的混频输入的输出，用于提供RF混频信号。

公开(公告)号：US07759915B2

公开(公告)日：2010-07-20

申请号：US11362982

申请日：2006-02-27

Applicant: Ramkishore Ganti ,  Caiyi Wang ,  Augusto M. Marques

Inventor： Ramkishore Ganti ,  Caiyi Wang ,  Augusto M. Marques

IPC: G05F1/00

CPC classification number: G05F1/56 ,  H02M3/155 ,  H02M2001/0045

Abstract: An apparatus comprises a circuit having a power supply node and a linear regulator configured to provide a regulated voltage at the power supply node of the circuit. The apparatus further comprises a switching regulator configured to provide input power to the linear regulator from a power source such as a battery. In some implementations, the circuit is a transceiver circuit.

Abstract translation: 一种装置包括具有电源节点的电路和被配置为在电路的电源节点处提供调节电压的线性调节器。 该装置还包括开关调节器，其被配置为从诸如电池的电源向线性调节器提供输入功率。 在一些实现中，电路是收发器电路。

公开(公告)号：US20080272837A1

公开(公告)日：2008-11-06

申请号：US11930804

申请日：2007-10-31

Applicant: David R. Welland ,  Donald A. Kerth ,  Caiyi Wang

Inventor： David R. Welland ,  Donald A. Kerth ,  Caiyi Wang

IPC: H03K5/00

CPC classification number: H05K9/00 ,  H03L7/18 ,  H05K1/0216 ,  H05K3/10 ,  Y10T29/49124

Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

Abstract translation: 提供一种减少电路干扰的方法和装置。 提供管理策略，以减少参考杂散和电路干扰。 管理策略使用一种或多种减少数字电流，最小化互感，利用场消除，防止泄漏电流和/或管理阻抗的技术的组合。 这些技术可以单独使用，或者优选地彼此组合使用。

公开(公告)号：US07376399B2

公开(公告)日：2008-05-20

申请号：US11096134

申请日：2005-03-31

Applicant: David R. Welland ,  Caiyi Wang

Inventor： David R. Welland ,  Caiyi Wang

IPC: H04B1/04 ,  H03C3/02 ,  H04B1/40

CPC classification number: H04B1/403

Abstract: Mixing circuitry for quadrature processing in communication systems and related methods are disclosed. The weighted mixing circuitry allows for arbitrary dividers to be utilized in generating the mixing signals for quadrature processing and thereby provides a significant advantage over prior architectures where 90 degree offset I and Q mixing signals were needed for quadrature mixing.

Abstract translation: 公开了用于通信系统中的正交处理的混合电路及相关方法。 加权混合电路允许任意的分频器用于生成用于正交处理的混合信号，并且因此提供了相对于其中需要90度偏移I和Q混合信号以进行正交混合的现有架构的显着优点。

公开(公告)号：US06993314B2

公开(公告)日：2006-01-31

申请号：US10074591

申请日：2002-02-13

Applicant: Lysander Lim ,  Caiyi Wang ,  David R. Welland ,  Donald A. Kerth ,  Richard T. Behrens ,  Jeffrey W. Scott ,  G. Diwakar Vishakhadatta ,  G. Tyson Tuttle ,  Vishnu S. Srinivasan

Inventor： Lysander Lim ,  Caiyi Wang ,  David R. Welland ,  Donald A. Kerth ,  Richard T. Behrens ,  Jeffrey W. Scott ,  G. Diwakar Vishakhadatta ,  G. Tyson Tuttle ,  Vishnu S. Srinivasan

IPC: H04N1/28

CPC classification number: H04B1/0003 ,  H03L7/085 ,  H03L7/087 ,  H03L7/091 ,  H03L7/099 ,  H03L7/187 ,  H03L7/199 ,  H03L7/23 ,  H04B1/28 ,  H04B1/406 ,  H04B15/02 ,  H04B15/04 ,  H04B2215/064

Abstract: A radio-frequency (RF) apparatus capable of transmitting RF signals includes transmitter path circuitry. The transmitter path circuitry includes a voltage-controlled oscillator (VCO) circuitry. The VCO circuitry generates a first signal that has a first frequency. A divider circuitry couples to the VCO circuitry and, in response to the first signal, the divider circuitry generates a second signal that has a second frequency. The frequency of the second signal equals the frequency of the first signal divided by a number.

公开(公告)号：US20050266817A1

公开(公告)日：2005-12-01

申请号：US11180267

申请日：2005-07-13

Applicant: David Welland ,  Caiyi Wang

Inventor： David Welland ,  Caiyi Wang

IPC: H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H03L7/193 ,  H03L7/199 ,  H03L7/23 ,  H04B1/06 ,  H04B1/40 ,  H04B7/00

CPC classification number: H03L7/193 ,  H03J2200/10 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H03L7/199 ,  H03L7/23 ,  H03L2207/06

Abstract: A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. During fine tuning adjustment, the PLL may be controlled by a plurality of analog control signals. The analog control signals may be derived by first generating a plurality of phase shifted signals from a divided version of the VCO output clock. Second, the phase differences between the plurality of phase shifted signals and a divided version of a reference clock may be detected and then converted to the analog control signals.

Abstract translation: 用于合成诸如无线通信信号的高频信号的方法和装置包括具有可变电容电压控制振荡器（VCO）的锁相环（PLL）频率合成器，其具有连续变量的离散可变电容 电容。 离散可变电容可以提供可变电容的粗调谐调整，以补偿电容器和电感器公差，并将输出频率调整为接近期望的频率输出。 连续可变电容可以提供可变电容的微调调整，以将输出频率聚焦以精确地匹配期望的频率输出。 在微调调整期间，PLL可以由多个模拟控制信号控制。 可以通过首先从VCO输出时钟的分割版本产生多个相移信号来导出模拟控制信号。 第二，可以检测多个相移信号和参考时钟的分割版本之间的相位差，然后转换成模拟控制信号。

公开(公告)号：US20050024509A1

公开(公告)日：2005-02-03

申请号：US10862488

申请日：2004-06-07

Applicant: Nadi Itani ,  Caiyi Wang ,  David Welland

Inventor： Nadi Itani ,  Caiyi Wang ,  David Welland

IPC: G06T5/40 ,  H04N5/235 ,  H04N5/243 ,  H04N5/351 ,  H04N5/378 ,  H04N5/20

CPC classification number: H04N5/2352

Abstract: An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a histogram-based automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit and a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC, as well as shutter timing for shutter gain.

Abstract translation: 用于电荷耦合器件（CCD）或CMOS成像系统的图像处理器系统包括基于直方图的自动增益控制（AGC）电路，其首先通过调整所述CCD系统来控制增益，然后对于较高的增益电平进行增益，使所述 CDSVGA电路和数字增益电路，以产生组合的目标增益电平。 一种用于成像器件的处理系统包括用于产生成像器信号的相机系统，用于从成像器接收数据的相关双样本（CDS）电路，可变增益放大器（VGA），模数转换器（ADC） 耦合到所述CDS电路，耦合到所述ADC的数字增益电路（DGC）以及耦合到所述DGC的用于控制CDS电路和DGC的自动增益控制（AGC）电路以及用于快门增益的快门定时。

公开(公告)号：US06574288B1

公开(公告)日：2003-06-03

申请号：US09087012

申请日：1998-05-29

Applicant: David R. Welland ,  Caiyi Wang

Inventor： David R. Welland ,  Caiyi Wang

IPC: H04B106

CPC classification number: H03L7/199 ,  H03J2200/10 ,  H03L7/099 ,  H03L7/113

Abstract: A method and apparatus for synthesizing high-frequency signals is disclosed that overcomes integration problem associated with prior implementations while meeting demanding phase noise and other impurity requirements. In one embodiment, a phase-locked loop (PLL) frequency synthesizer is disclosed having a voltage controlled oscillator (VCO) with a variable capacitance that includes a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance, and the continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance. In a further detail, discrete control circuitry is disclosed that provides a digital control signal to a discretely variable capacitance circuit to control its overall capacitance and that adjusts the digital control signal depending upon feedback from the output frequency.

Abstract translation: 公开了一种用于合成高频信号的方法和装置，其克服了与现有实施相关的集成问题，同时满足苛刻的相位噪声和其他杂质要求。 在一个实施例中，公开了具有可变电容的压控振荡器（VCO）的锁相环（PLL）频率合成器，该可变电容包括连续可变电容的离散可变电容。 离散可变电容可以提供可变电容的粗调谐调节，并且连续可变电容可以提供可变电容的精细调谐。 更详细地，公开了离散控制电路，其向离散可变电容电路提供数字控制信号以控制其整体电容，并且根据来自输出频率的反馈来调整数字控制信号。

公开(公告)号：US08354947B2

公开(公告)日：2013-01-15

申请号：US13025171

申请日：2011-02-11

Applicant: Hsiang-Hui Chang ,  Caiyi Wang ,  George Chien ,  Hsin-Hung Chen ,  Chih-Jung Chen

Inventor： Hsiang-Hui Chang ,  Caiyi Wang ,  George Chien ,  Hsin-Hung Chen ,  Chih-Jung Chen

IPC: H03M3/00

CPC classification number: H03M3/344 ,  H03M3/436 ,  H03M3/50 ,  H03M7/3042

Abstract: One signal processing apparatus includes a sigma-delta modulating block and a notch filtering block. The sigma-delta modulating block is arranged to perform a sigma-delta modulation upon a signal input and accordingly generate a signal output. The notch filtering block is arranged to perform a notch filtering operation upon the signal output for generating a filtered signal output. Another signal processing apparatus includes a sigma-delta modulating block and a notch filtering block. The sigma-delta modulating block is arranged to perform a sigma-delta modulation upon a signal input and accordingly generate a signal output. The notch filtering block is enabled for performing a notch filtering operation upon the signal output when the signal processing apparatus operates in a first operational mode, and the notch filtering block is disabled when the signal processing apparatus operates in a second operational mode.

Abstract translation: 一个信号处理装置包括Σ-Δ调制块和陷波滤波块。 Σ-Δ调制块被布置成在信号输入端执行Σ-Δ调制，从而产生信号输出。 陷波滤波块被布置成在信号输出上执行陷波滤波操作以产生滤波信号输出。 另一信号处理装置包括Σ-Δ调制块和陷波滤波块。 Σ-Δ调制块被布置成在信号输入端执行Σ-Δ调制，从而产生信号输出。 当信号处理装置在第一操作模式下操作时，陷波滤波块被使能以对信号输出执行陷波滤波操作，并且当信号处理装置在第二操作模式下操作时，陷波滤波块被禁用。

公开(公告)号：US20120074993A1

公开(公告)日：2012-03-29

申请号：US13273231

申请日：2011-10-14

Applicant: Yen-Horng Chen ,  Augusto Marques ,  Caiyi Wang

Inventor： Yen-Horng Chen ,  Augusto Marques ,  Caiyi Wang

IPC: H03L7/08

CPC classification number: H03L7/099 ,  H03L1/00 ,  H03L1/02 ,  H03L2207/06 ,  H03L2207/50

Abstract: An integrated circuit device includes at least one controllable oscillator including a first control port and at least one further control port, at least one frequency control module including an output arranged to provide a frequency control signal. The at least one controllable oscillator further includes at least one compensation module including an output arranged to provide at least one compensation signal. The at least one compensation module includes an integrator component arranged to receive at an input thereof a signal that is representative of a difference between the indication of the frequency control signal and a reference signal, and to output an integrated difference signal. The at least one compensation module is arranged to generate the at least one compensation signal based at least partly on the integrated difference signal output by the integrator component.

Abstract translation: 集成电路装置包括至少一个包括第一控制端口和至少一个另外的控制端口的可控振荡器，至少一个频率控制模块，其包括布置成提供频率控制信号的输出。 所述至少一个可控振荡器还包括至少一个补偿模块，该补偿模块包括布置成提供至少一个补偿信号的输出。 所述至少一个补偿模块包括积分器部件，其被布置为在其输入处接收表示所述频率控制信号的指示与参考信号之间的差异的信号，并输出积分差分信号。 至少一个补偿模块被布置成至少部分地基于由积分器组件输出的积分差分信号来产生至少一个补偿信号。