公开(公告)号：US09048259B2

公开(公告)日：2015-06-02

申请号：US13562805

申请日：2012-07-31

Applicant: Shih-Ting Hung ,  Cheng-Hung Chang ,  Chen-Yi Lee ,  Chen-Nan Yeh ,  Chen-Hua Yu

Inventor： Shih-Ting Hung ,  Cheng-Hung Chang ,  Chen-Yi Lee ,  Chen-Nan Yeh ,  Chen-Hua Yu

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L21/76202 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/1083 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure includes a semiconductor substrate having a first portion and a second portion. A first Fin field-effect transistor (FinFET) is formed over the first portion of the semiconductor substrate, wherein the first FinFET includes a first fin having a first fin height. A second FinFET is formed over the second portion of the semiconductor substrate, wherein the second FinFET includes a second fin having a second fin height different from the first fin height. A top surface of the first fin is substantially level with a top surface of the second fin. A punch-through stopper is underlying and adjoining the first FinFET, wherein the punch-through stopper isolates the first fin from the first portion of the semiconductor substrate.

Abstract translation: 半导体结构包括具有第一部分和第二部分的半导体衬底。 第一Fin场效应晶体管（FinFET）形成在半导体衬底的第一部分上，其中第一FinFET包括具有第一鳍片高度的第一鳍片。 第二FinFET形成在半导体衬底的第二部分上，其中第二FinFET包括具有不同于第一鳍片高度的第二鳍片高度的第二鳍片。 第一翅片的顶表面基本上与第二翅片的顶表面平齐。 穿通止动件位于第一FinFET的下面并邻接，其中穿通止动件将第一鳍片与半导体衬底的第一部分隔离。

公开(公告)号：US20120299110A1

公开(公告)日：2012-11-29

申请号：US13562805

申请日：2012-07-31

Applicant: Shih-Ting Hung ,  Cheng-Hung Chang ,  Chen-Yi Lee ,  Chen-Nan Yeh ,  Chen-Hua Yu

Inventor： Shih-Ting Hung ,  Cheng-Hung Chang ,  Chen-Yi Lee ,  Chen-Nan Yeh ,  Chen-Hua Yu

IPC: H01L27/088

CPC classification number: H01L21/76202 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/1083 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure includes a semiconductor substrate having a first portion and a second portion. A first Fin field-effect transistor (FinFET) is formed over the first portion of the semiconductor substrate, wherein the first FinFET includes a first fin having a first fin height. A second FinFET is formed over the second portion of the semiconductor substrate, wherein the second FinFET includes a second fin having a second fin height different from the first fin height. A top surface of the first fin is substantially level with a top surface of the second fin. A punch-through stopper is underlying and adjoining the first FinFET, wherein the punch-through stopper isolates the first fin from the first portion of the semiconductor substrate.

Abstract translation: 半导体结构包括具有第一部分和第二部分的半导体衬底。 第一Fin场效应晶体管（FinFET）形成在半导体衬底的第一部分上，其中第一FinFET包括具有第一鳍片高度的第一鳍片。 第二FinFET形成在半导体衬底的第二部分上，其中第二FinFET包括具有不同于第一鳍片高度的第二鳍片高度的第二鳍片。 第一翅片的顶表面基本上与第二翅片的顶表面平齐。 穿通止动件位于第一FinFET的下面并邻接，其中穿通止动件将第一鳍片与半导体衬底的第一部分隔离。

公开(公告)号：US20120261827A1

公开(公告)日：2012-10-18

申请号：US13085668

申请日：2011-04-13

Applicant: Chen-Hua YU ,  Cheng-Hung CHANG ,  Ebin LIAO ,  Chia-Lin YU ,  Hsiang-Yi WANG ,  Chun Hua CHANG ,  Li-Hsien HUANG ,  Darryl KUO ,  Tsang-Jiuh WU ,  Wen-Chih CHIOU

Inventor： Chen-Hua YU ,  Cheng-Hung CHANG ,  Ebin LIAO ,  Chia-Lin YU ,  Hsiang-Yi WANG ,  Chun Hua CHANG ,  Li-Hsien HUANG ,  Darryl KUO ,  Tsang-Jiuh WU ,  Wen-Chih CHIOU

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/30625 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76844 ,  H01L21/76846 ,  H01L23/481 ,  H01L23/49827 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor component includes a semiconductor substrate having a top surface. An opening extends from the top surface into the semiconductor substrate. The opening includes an interior surface. A first dielectric liner having a first compressive stress is disposed on the interior surface of the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner. A metal barrier layer is disposed on the third dielectric liner. A conductive material is disposed on the metal barrier layer and fills the opening.

Abstract translation: 半导体部件包括具有顶面的半导体基板。 开口从顶表面延伸到半导体衬底中。 开口包括内表面。 具有第一压缩应力的第一电介质衬垫设置在开口的内表面上。 具有拉伸应力的第二电介质衬垫设置在第一电介质衬垫上。 具有设置在第二电介质衬垫上的第二压缩应力的第三绝缘衬垫。 金属阻挡层设置在第三电介质衬垫上。 导电材料设置在金属阻挡层上并填充开口。

公开(公告)号：US07939889B2

公开(公告)日：2011-05-10

申请号：US11873156

申请日：2007-10-16

Applicant: Chen-Hua Yu ,  Yu-Rung Hsu ,  Chen-Nan Yeh ,  Cheng-Hung Chang

Inventor： Chen-Hua Yu ,  Yu-Rung Hsu ,  Chen-Nan Yeh ,  Cheng-Hung Chang

IPC: H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC classification number: H01L29/1033 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure includes a semiconductor fin on a top surface of a substrate, wherein the semiconductor fin includes a middle section having a first width; and a first and a second end section connected to opposite ends of the middle section, wherein the first and the second end sections each comprises at least a top portion having a second width greater than the first width. The semiconductor structure further includes a gate dielectric layer on a top surface and sidewalls of the middle section of the semiconductor fin; and a gate electrode on the gate dielectric layer.

Abstract translation: 半导体结构包括在基板的顶面上的半导体翅片，其中半导体鳍片包括具有第一宽度的中间部分; 以及连接到中间部分的相对端部的第一和第二端部分，其中第一和第二端部部分至少包括具有大于第一宽度的第二宽度的顶部部分。 半导体结构还包括在半导体鳍片的顶表面和中间部分的侧壁上的栅介质层; 以及栅极电介质层上的栅电极。

公开(公告)号：US20100276761A1

公开(公告)日：2010-11-04

申请号：US12652947

申请日：2010-01-06

Applicant: Chih-Hang Tung ,  Chin-Hsiang Lin ,  Cheng-Hung Chang ,  Sey-Ping Sun

Inventor： Chih-Hang Tung ,  Chin-Hsiang Lin ,  Cheng-Hung Chang ,  Sey-Ping Sun

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7856 ,  H01L29/41791 ,  H01L29/66803 ,  H01L29/7839 ,  H01L29/785 ,  H01L2029/7858

Abstract: Non-planar transistors and methods of fabrication thereof are described. In an embodiment, a method of forming a non-planar transistor includes forming a channel region on a first portion of a semiconductor fin, the semiconductor fin having a top surface and sidewalls. A gate electrode is formed over the channel region of the semiconductor fin, and an in-situ doped semiconductor layer is grown on the top surface and the sidewalls of the semiconductor fin on opposing sides of the gate electrode using a selective epitaxial growth process. At least a part of the doped semiconductor layer is converted to form a dopant rich region.

Abstract translation: 描述了非平面晶体管及其制造方法。 在一个实施例中，形成非平面晶体管的方法包括在半导体鳍片的第一部分上形成沟道区域，所述半导体鳍片具有顶表面和侧壁。 在半导体鳍片的沟道区域上形成栅电极，并且使用选择性外延生长工艺在栅电极的相对侧的半导体翅片的顶表面和侧壁上生长原位掺杂半导体层。 掺杂半导体层的至少一部分被转换以形成掺杂剂浓度区域。

公开(公告)号：US20100221878A1

公开(公告)日：2010-09-02

申请号：US12777937

申请日：2010-05-11

Applicant: Chen-Hua Yu ,  Cheng-Tung Lin ,  Cheng-Hung Chang ,  Hsiang-Yi Wang ,  Chen-Nan Yeh

Inventor： Chen-Hua Yu ,  Cheng-Tung Lin ,  Cheng-Hung Chang ,  Hsiang-Yi Wang ,  Chen-Nan Yeh

IPC: H01L21/8238

CPC classification number: H01L21/823835 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092

Abstract: A semiconductor device and system for a hybrid metal fully silicided (FUSI) gate structure is disclosed. The semiconductor system comprises a PMOS gate structure, the PMOS gate structure including a first high-κ dielectric layer, a P-metal layer, a mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric layer, the P-metal layer and a fully silicided layer formed on the P-metal layer. The semiconductor system further comprises an NMOS gate structure, the NMOS gate structure includes a second high-κ dielectric layer, the fully silicided layer, and the mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric and the fully silicided layer.

Abstract translation: 公开了一种用于混合金属全硅化（FUSI）栅极结构的半导体器件和系统。 所述半导体系统包括PMOS栅极结构，所述PMOS栅极结构包括第一高<！ - SIPO < 介电层，P金属层，中间间隙金属层，其中中间间隙金属层形成在高金属层之间。 电介质层，P金属层和形成在P金属层上的完全硅化物层。 所述半导体系统还包括NMOS栅极结构，所述NMOS栅极结构包括第二高<！ - SIPO < 电介质层，完全硅化物层和中间间隙金属层，其中中间间隙金属层形成在高介电层之间。 电介质和完全硅化物层。

公开(公告)号：US20100163971A1

公开(公告)日：2010-07-01

申请号：US12347123

申请日：2008-12-31

Applicant: Shih-Ting Hung ,  Cheng-Hung Chang ,  Chen-Yi Lee ,  Chen-Nan Yeh ,  Chen-Hua Yu

Inventor： Shih-Ting Hung ,  Cheng-Hung Chang ,  Chen-Yi Lee ,  Chen-Nan Yeh ,  Chen-Hua Yu

IPC: H01L29/772

CPC classification number: H01L21/76202 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/1083 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure includes a semiconductor substrate having a first portion and a second portion. A first Fin field-effect transistor (FinFET) is formed over the first portion of the semiconductor substrate, wherein the first FinFET includes a first fin having a first fin height. A second FinFET is formed over the second portion of the semiconductor substrate, wherein the second FinFET includes a second fin having a second fin height different from the first fin height. A top surface of the first fin is substantially level with a top surface of the second fin. A punch-through stopper is underlying and adjoining the first FinFET, wherein the punch-through stopper isolates the first fin from the first portion of the semiconductor substrate.

Abstract translation: 半导体结构包括具有第一部分和第二部分的半导体衬底。 第一Fin场效应晶体管（FinFET）形成在半导体衬底的第一部分上，其中第一FinFET包括具有第一鳍片高度的第一鳍片。 第二FinFET形成在半导体衬底的第二部分上，其中第二FinFET包括具有不同于第一鳍片高度的第二鳍片高度的第二鳍片。 第一翅片的顶表面基本上与第二翅片的顶表面平齐。 穿通止动件位于第一FinFET的下面并邻接，其中穿通止动件将第一鳍片与半导体衬底的第一部分隔离。

公开(公告)号：US20100085033A1

公开(公告)日：2010-04-08

申请号：US12246982

申请日：2008-10-07

Applicant: Jui-Fang Chen ,  Cheng-Hung Chang ,  Chung-Jung Chen ,  Chien-Kuo Ko ,  Chi-Chun Yao

Inventor： Jui-Fang Chen ,  Cheng-Hung Chang ,  Chung-Jung Chen ,  Chien-Kuo Ko ,  Chi-Chun Yao

IPC: G01N27/00 ,  G21F5/00

CPC classification number: H01J37/3171 ,  H01J37/244 ,  H01J2237/022 ,  H01J2237/24405 ,  H01J2237/24564

Abstract: The invention provides an ion current measurement device for a tool having an ion source. The ion current measurement device comprises an ion collecting cup and a replaceable liner. The ion collecting cup is disposed in the tool and the ion collecting cup possesses a cup opening facing the ion source. The replaceable liner is disposed in the ion collecting cup and the replaceable liner entirely covers a continuous inner sidewall of the ion collecting cup.

Abstract translation: 本发明提供了一种用于具有离子源的工具的离子电流测量装置。 离子电流测量装置包括离子收集杯和可更换衬垫。 离子收集杯设置在工具中，离子收集杯具有面向离子源的杯形开口。 可替换的衬垫设置在离子收集杯中，并且可替换的衬套完全覆盖离子收集杯的连续的内侧壁。

公开(公告)号：US20090166567A1

公开(公告)日：2009-07-02

申请号：US12403191

申请日：2009-03-12

Applicant: Jui-Fang Chen ,  Cheng-Hung Chang ,  Chung-Jung Chen ,  Chih-Ming Yang ,  Chien-Kuo Ko

Inventor： Jui-Fang Chen ,  Cheng-Hung Chang ,  Chung-Jung Chen ,  Chih-Ming Yang ,  Chien-Kuo Ko

IPC: H01J37/08

CPC classification number: G21F1/12

Abstract: A method of performing an ion implantation is provided. A workpiece is installed in the ion implanter. A wafer is provided in a receiving space within an ion implanter. An ion beam is generated by an ion source of the ion implanter. The bombard of the ion beam is blocked and particles generated during or after conducting the step of generating the ion beam are collected by the workpiece.

Abstract translation: 提供了进行离子注入的方法。 工件安装在离子注入机中。 晶片设置在离子注入机内的接收空间中。 离子束由离子注入机的离子源产生。 离子束的轰击被阻挡，并且在进行产生离子束的步骤期间或之后产生的颗粒被工件收集。

公开(公告)号：US20090085126A1

公开(公告)日：2009-04-02

申请号：US11863804

申请日：2007-09-28

Applicant: Chen-Hua Yu ,  Cheng-Tung Lin ,  Cheng-Hung Chang ,  Hsiang-Yi Wang ,  Chen-Nan Yeh

Inventor： Chen-Hua Yu ,  Cheng-Tung Lin ,  Cheng-Hung Chang ,  Hsiang-Yi Wang ,  Chen-Nan Yeh

IPC: H01L29/00

CPC classification number: H01L21/823835 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092

Abstract: A semiconductor device and system for a hybrid metal fully silicided (FUSI) gate structure is disclosed. The semiconductor system comprises a PMOS gate structure, the PMOS gate structure including a first high-κ dielectric layer, a P-metal layer, a mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric layer, the P-metal layer and a fully silicided layer formed on the P-metal layer. The semiconductor system further comprises an NMOS gate structure, the NMOS gate structure includes a second high-κ dielectric layer, the fully silicided layer, and the mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric and the fully silicided layer.

Abstract translation: 公开了一种用于混合金属全硅化（FUSI）栅极结构的半导体器件和系统。 半导体系统包括PMOS栅极结构，PMOS栅极结构包括第一高k电介质层，P金属层，中间间隙金属层，其中中间间隙金属层形成在高k电介质 层，P金属层和形成在P金属层上的完全硅化物层。 半导体系统还包括NMOS栅极结构，NMOS栅极结构包括第二高k电介质层，完全硅化层和中间间隙金属层，其中中间间隙金属层形成在高kappa 电介质和完全硅化物层。