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    III-nitride based semiconductor structure with multiple conductive tunneling layer
    3.
    发明授权
    III-nitride based semiconductor structure with multiple conductive tunneling layer 有权
    具有多个导电隧穿层的III族氮化物基半导体结构

    公开(公告)号：US08519414B2

    公开(公告)日：2013-08-27

    申请号：US13237181

    申请日：2011-09-20

    Applicant: Chia-Lin Yu ,  Ding-Yuan Chen ,  Chen-Hua Yu ,  Wen-Chih Chiou

    Inventor： Chia-Lin Yu ,  Ding-Yuan Chen ,  Chen-Hua Yu ,  Wen-Chih Chiou

    IPC: H01L27/15

    CPC classification number: H01L33/04 ,  H01L33/12 ,  H01L33/32

    Abstract: A semiconductor structure includes a substrate and a conductive carrier-tunneling layer over and contacting the substrate. The conductive carrier-tunneling layer includes first group-III nitride (III-nitride) layers having a first bandgap, wherein the first III-nitride layers have a thickness less than about 5 nm; and second III-nitride layers having a second bandgap lower than the first bandgap, wherein the first III-nitride layers and the second III-nitride layers are stacked in an alternating pattern. The semiconductor structure is free from a III-nitride layer between the substrate and the conductive carrier-tunneling layer. The semiconductor structure further includes an active layer over the conductive carrier-tunneling layer.

    Abstract translation: 半导体结构包括衬底和与衬底接触的导电载体隧穿层。 导电载体隧穿层包括具有第一带隙的第一III族氮化物（III族氮化物）层，其中第一III族氮化物层具有小于约5nm的厚度; 和具有比第一带隙低的第二带隙的第二III族氮化物层，其中第一III族氮化物层和第二III族氮化物层以交替图案堆叠。 半导体结构在衬底和导电载体 - 隧穿层之间不含III族氮化物层。 半导体结构还包括在导电载体 - 隧穿层上的有源层。

    III-Nitride Based Semiconductor Structure with Multiple Conductive Tunneling Layer
    7.
    发明申请
    III-Nitride Based Semiconductor Structure with Multiple Conductive Tunneling Layer 有权
    基于III型氮化物的多导体隧穿层半导体结构

    公开(公告)号：US20120007048A1

    公开(公告)日：2012-01-12

    申请号：US13237181

    申请日：2011-09-20

    Applicant: Chia-Lin Yu ,  Ding-Yuan Chen ,  Chen-Hua Yu ,  Wen-Chih Chiou

    Inventor： Chia-Lin Yu ,  Ding-Yuan Chen ,  Chen-Hua Yu ,  Wen-Chih Chiou

    IPC: H01L29/12 ,  H01L21/20

    CPC classification number: H01L33/04 ,  H01L33/12 ,  H01L33/32

    Abstract: A semiconductor structure includes a substrate and a conductive carrier-tunneling layer over and contacting the substrate. The conductive carrier-tunneling layer includes first group-III nitride (III-nitride) layers having a first bandgap, wherein the first III-nitride layers have a thickness less than about 5 nm; and second III-nitride layers having a second bandgap lower than the first bandgap, wherein the first III-nitride layers and the second III-nitride layers are stacked in an alternating pattern. The semiconductor structure is free from a III-nitride layer between the substrate and the conductive carrier-tunneling layer. The semiconductor structure further includes an active layer over the conductive carrier-tunneling layer.

    Abstract translation: 半导体结构包括衬底和与衬底接触的导电载体隧穿层。 导电载体隧穿层包括具有第一带隙的第一III族氮化物（III族氮化物）层，其中第一III族氮化物层具有小于约5nm的厚度; 和具有比第一带隙低的第二带隙的第二III族氮化物层，其中第一III族氮化物层和第二III族氮化物层以交替图案堆叠。 半导体结构在衬底和导电载体 - 隧穿层之间不含III族氮化物层。 半导体结构还包括在导电载体 - 隧穿层上的有源层。

    Vertical III-Nitride Light Emitting Diodes on Patterned Substrates with Embedded Bottom Electrodes
    8.
    发明申请
    Vertical III-Nitride Light Emitting Diodes on Patterned Substrates with Embedded Bottom Electrodes 审中-公开
    垂直III型氮化物发光二极管在嵌有底部电极的图案衬底上

    公开(公告)号：US20100012954A1

    公开(公告)日：2010-01-21

    申请号：US12191033

    申请日：2008-08-13

    Applicant: Chen-Hua Yu ,  Chia-Lin Yu ,  Wen-Chih Chiou ,  Ding-Yuan Chen ,  Hung-Ta Lin

    Inventor： Chen-Hua Yu ,  Chia-Lin Yu ,  Wen-Chih Chiou ,  Ding-Yuan Chen ,  Hung-Ta Lin

    IPC: H01L33/00 ,  H01L21/00

    CPC classification number: H01L33/382 ,  H01L33/007 ,  H01L33/0079 ,  H01L33/14 ,  H01L33/38 ,  H01L2933/0016

    Abstract: A light emitting diode (LED) device is presented. The LED device includes a substrate, a layered LED structure, and an embedded bottom electrode. The layered LED structure includes a buffer/nucleation layer disposed on the substrate, an active layer, and a top-side contact. A first-contact III-nitride layer is interposed between the buffer/nucleation layer and the active layer. A second-contact III-nitride layer is interposed between the active well layer and the top-side contact. A bottom electrode extends through the substrate, through the buffer/nucleation layer and terminates within the first-contact III-nitride layer.

    Abstract translation: 提出了一种发光二极管（LED）装置。 LED器件包括衬底，层状LED结构和嵌入式底部电极。 分层LED结构包括设置在基板上的缓冲/成核层，有源层和顶侧接触。 第一接触III族氮化物层介于缓冲层/成核层与有源层之间。 第二接触III族氮化物层介于活性阱层和顶侧接触之间。 底部电极延伸通过衬底，通过缓冲/成核层并终止于第一接触III族氮化物层内。

    Light-emitting diodes on concave texture substrate
    9.
    发明授权
    Light-emitting diodes on concave texture substrate 有权
    凹面纹理基板上的发光二极管

    公开(公告)号：US08629465B2

    公开(公告)日：2014-01-14

    申请号：US13358327

    申请日：2012-01-25

    Applicant: Chen-Hua Yu ,  Hung-Ta Lin ,  Wen-Chih Chiou ,  Ding-Yuan Chen ,  Chia-Lin Yu

    Inventor： Chen-Hua Yu ,  Hung-Ta Lin ,  Wen-Chih Chiou ,  Ding-Yuan Chen ,  Chia-Lin Yu

    IPC: H01L33/08

    CPC classification number: H01L33/48 ,  H01L33/20 ,  H01L33/24

    Abstract: A semiconductor device having light-emitting diodes (LEDs) formed on a concave textured substrate is provided. A substrate is patterned and etched to form recesses. A separation layer is formed along the bottom of the recesses. An LED structure is formed along the sidewalls and, optionally, along the surface of the substrate between adjacent recesses. In these embodiments, the surface area of the LED structure is increased as compared to a planar surface. In another embodiment, the LED structure is formed within the recesses such that the bottom contact layer is non-conformal to the topology of the recesses. In these embodiments, the recesses in a silicon substrate result in a cubic structure in the bottom contact layer, such as an n-GaN layer, which has a non-polar characteristic and exhibits higher external quantum efficiency.

    Abstract translation: 提供了一种形成在凹面纹理基板上的发光二极管（LED）的半导体器件。 对衬底进行图案化和蚀刻以形成凹陷。 沿着凹部的底部形成分离层。 沿着侧壁和任选地沿着相邻凹部之间的基板的表面形成LED结构。 在这些实施例中，与平面表面相比，LED结构的表面积增加。 在另一个实施例中，LED结构形成在凹部内，使得底部接触层与凹部的拓扑不一致。 在这些实施例中，硅衬底中的凹槽导致底接触层中的立方结构，例如具有非极性特性并且表现出更高外部量子效率的n-GaN层。

    Through silicon via (TSV) isolation structures for noise reduction in 3D integrated circuit
    10.
    发明授权
    Through silicon via (TSV) isolation structures for noise reduction in 3D integrated circuit 有权
    通过硅通孔（TSV）隔离结构降低3D集成电路

    公开(公告)号：US08546953B2

    公开(公告)日：2013-10-01

    申请号：US13324405

    申请日：2011-12-13

    Applicant: Jaw-Juinn Horng ,  Chia-Lin Yu ,  Chung-Hui Chen ,  Der-Chyang Yeh ,  Yung-Chow Peng

    Inventor： Jaw-Juinn Horng ,  Chia-Lin Yu ,  Chung-Hui Chen ,  Der-Chyang Yeh ,  Yung-Chow Peng

    IPC: H01L23/48 ,  H01L29/40 ,  H01L23/04 ,  H01L21/44

    CPC classification number: H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Through silicon via (TSV) isolation structures are provided and suppress electrical noise such as may be propagated through a semiconductor substrate when caused by a signal carrying active TSV such as used in 3D integrated circuit packaging. The isolation TSV structures are surrounded by an oxide liner and surrounding dopant impurity regions. The surrounding dopant impurity regions may be P-type dopant impurity regions that are coupled to ground or N-type dopant impurity regions that may advantageously be coupled to VDD. The TSV isolation structure is advantageously disposed between an active, signal carrying TSV and active semiconductor devices and the TSV isolation structures may be formed in an array that isolates an active, signal carrying TSV structure from active semiconductor devices.

    Abstract translation: 提供通过硅通孔（TSV）隔离结构，并且抑制诸如在由3D集成电路封装中使用的携带有源TSV的信号引起的时候可能传播通过半导体衬底的电噪声。 隔离TSV结构被氧化物衬垫和周围的掺杂剂杂质区包围。 周围的掺杂剂杂质区域可以是耦合到接地的P型掺杂剂杂质区域或者可以有利地连接到VDD的N型掺杂剂杂质区域。 TSV隔离结构有利地设置在有源信号承载TSV和有源半导体器件之间，并且TSV隔离结构可以形成为将有源信号传输TSV结构与有源半导体器件隔离的阵列。

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