公开(公告)号：US08803322B2

公开(公告)日：2014-08-12

申请号：US13272506

申请日：2011-10-13

申请人： Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Yi-Hsiu Chen ,  Ebin Liao ,  Yuan-Hung Liu ,  Wen-Chih Chiou

发明人： Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Yi-Hsiu Chen ,  Ebin Liao ,  Yuan-Hung Liu ,  Wen-Chih Chiou

IPC分类号： H01L23/48

CPC分类号： H01L23/5226 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L2224/05006 ,  H01L2224/05009 ,  H01L2224/05546 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

摘要： The embodiments of forming a through substrate via (TSV) structure described enable reducing risk of damaging gate structures due to over polishing of an inter-level dielectric layer (ILD) layer. The TSV structure with a wider opening near one end also enables better gapfill.

摘要翻译： 形成通过（TSV）通孔的结构的实施例能够降低由于层间电介质层（ILD）层的过度抛光而损坏栅极结构的风险。 在一端附近具有较宽开口的TSV结构还可实现更好的间隙填充。

公开(公告)号：US08729695B2

公开(公告)日：2014-05-20

申请号：US13497611

申请日：2009-09-25

申请人： Chirayarikathu Veedu Sankarapillai Premachandran ,  Rakesh Kumar ,  Nagarajan Ranganathan ,  Won Kyoung Choi ,  Ebin Liao ,  Yasuyuki Mitsuoka ,  Hiroshi Takahashi ,  Ryuta Mitsusue

发明人： Chirayarikathu Veedu Sankarapillai Premachandran ,  Rakesh Kumar ,  Nagarajan Ranganathan ,  Won Kyoung Choi ,  Ebin Liao ,  Yasuyuki Mitsuoka ,  Hiroshi Takahashi ,  Ryuta Mitsusue

IPC分类号： H01L23/12 ,  H01L21/00

CPC分类号： H01L21/6836 ,  B81B2207/092 ,  B81B2207/093 ,  B81B2207/097 ,  B81C2203/019 ,  H01L24/48 ,  H01L24/94 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/16195 ,  H01L2924/16235 ,  H01L2924/16315 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In an embodiment, a wafer level package may be provided. The wafer level package may include a device wafer including a MEMS device, a cap wafer disposed over the device wafer, at least one first interconnect disposed between the device wafer and the cap wafer and configured to provide an electrical connection between the device wafer and the cap wafer, and a conformal sealing ring disposed between the device wafer and the cap wafer and configured to surround the at least one first interconnect and the MEMS device so as to provide a conformally sealed environment for the at least one first interconnect and the MEMS device, wherein the conformal sealing ring may be configured to conform to a respective suitable surface of the device wafer and the cap wafer when the device wafer may be bonded to the cap wafer. A method of forming a wafer level package may also be provided.

摘要翻译： 在一个实施例中，可以提供晶片级封装。 晶片级封装可以包括包括MEMS器件的器件晶片，设置在器件晶片上的帽晶片，设置在器件晶片和帽晶片之间的至少一个第一互连，并且被配置为在器件晶片和晶片级封装之间提供电连接 帽状晶片和保形密封环，其设置在器件晶片和盖晶片之间并且被配置为围绕至少一个第一互连和MEMS器件，以便为至少一个第一互连和MEMS器件提供保形密封的环境 ，其中所述保形密封环可以被配置为当所述器件晶片可以结合到所述盖晶片时，使其符合所述器件晶片和所述盖晶片的相应合适的表面。 还可以提供一种形成晶片级封装的方法。

公开(公告)号：US20130037603A1

公开(公告)日：2013-02-14

申请号：US13578407

申请日：2010-02-10

申请人： Won Kyoung Choi ,  Chiraharikathu Veedu Sankarapillai Premachandran ,  Ling Xie ,  Ebin Liao ,  Siong Chiew Joe Ong ,  Kewu Bai

发明人： Won Kyoung Choi ,  Chiraharikathu Veedu Sankarapillai Premachandran ,  Ling Xie ,  Ebin Liao ,  Siong Chiew Joe Ong ,  Kewu Bai

IPC分类号： B23K1/20

CPC分类号： H01L23/49816 ,  H01L23/49866 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/29101 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/32145 ,  H01L2224/83193 ,  H01L2224/83801 ,  H01L2224/8381 ,  H01L2224/83825 ,  H01L2224/83894 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/1461 ,  H01L2924/351 ,  H05K3/3463 ,  H05K2201/0338 ,  H01L2924/00 ,  H01L2924/3512

摘要： In an embodiment, a method of forming a bonded structure is provided. The method may include forming at least one first under bump metallurgy (UBM) structure on a first substrate, forming a first gold layer on the at least one first under bump metallurgy structure; forming a tin layer on the first gold layer, forming an indium layer on the tin layer, forming an inhibition layer configured to inhibit oxygen penetration on the indium layer, and forming at least one second under bump metallurgy structure on a second substrate, forming s second gold layer on the at least one second under bump metallurgy structure; and bringing the inhibition layer into contact with the second gold layer at a predetermined temperature to form a resultant intermetallic structure between the first substrate and the second substrate thereby bonding the first substrate to the second substrate and forming the bonded structure.

摘要翻译： 在一个实施例中，提供了形成接合结构的方法。 该方法可以包括在第一衬底上形成至少一个第一凸点下金属（UBM）结构，在该至少一个第一凸点下金属结构上形成第一金层; 在所述第一金层上形成锡层，在所述锡层上形成铟层，形成抑制氧层在所述铟层上的渗透的抑制层，以及在第二基板上形成至少一个第二凸块下金属结构，形成s 在所述至少一个第二凸块下金属结构上的第二金层; 并且使所述抑制层与所述第二金层在预定温度下接触以在所述第一基板和所述第二基板之间形成所得的金属间结构，从而将所述第一基板接合到所述第二基板并形成所述接合结构。

公开(公告)号：US20120261827A1

公开(公告)日：2012-10-18

申请号：US13085668

申请日：2011-04-13

申请人： Chen-Hua YU ,  Cheng-Hung CHANG ,  Ebin LIAO ,  Chia-Lin YU ,  Hsiang-Yi WANG ,  Chun Hua CHANG ,  Li-Hsien HUANG ,  Darryl KUO ,  Tsang-Jiuh WU ,  Wen-Chih CHIOU

发明人： Chen-Hua YU ,  Cheng-Hung CHANG ,  Ebin LIAO ,  Chia-Lin YU ,  Hsiang-Yi WANG ,  Chun Hua CHANG ,  Li-Hsien HUANG ,  Darryl KUO ,  Tsang-Jiuh WU ,  Wen-Chih CHIOU

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/30625 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76844 ,  H01L21/76846 ,  H01L23/481 ,  H01L23/49827 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor component includes a semiconductor substrate having a top surface. An opening extends from the top surface into the semiconductor substrate. The opening includes an interior surface. A first dielectric liner having a first compressive stress is disposed on the interior surface of the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner. A metal barrier layer is disposed on the third dielectric liner. A conductive material is disposed on the metal barrier layer and fills the opening.

摘要翻译： 半导体部件包括具有顶面的半导体基板。 开口从顶表面延伸到半导体衬底中。 开口包括内表面。 具有第一压缩应力的第一电介质衬垫设置在开口的内表面上。 具有拉伸应力的第二电介质衬垫设置在第一电介质衬垫上。 具有设置在第二电介质衬垫上的第二压缩应力的第三绝缘衬垫。 金属阻挡层设置在第三电介质衬垫上。 导电材料设置在金属阻挡层上并填充开口。

公开(公告)号：US20120074582A1

公开(公告)日：2012-03-29

申请号：US12892409

申请日：2010-09-28

申请人： Chen-Hua YU ,  Wen-Chih CHIOU ,  Ebin LIAO ,  Tsang-Jiuh WU

发明人： Chen-Hua YU ,  Wen-Chih CHIOU ,  Ebin LIAO ,  Tsang-Jiuh WU

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L21/76831 ,  H01L21/486 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00

摘要： A device with through-silicon via (TSV) and a method of forming the same includes the formation of an opening in a silicon substrate, the formation of a first insulation layer on the sidewalls and bottom of the opening, the formation of a second insulation layer on the sidewalls and bottom of the opening. A first interface between the first insulation layer and the silicon substrate has an interface roughness with a peak-to-valley height less than 5 nm. A second interface between the second insulation layer and the conductive layer has an interface roughness with a peak-to-valley height less than 5 nm.

摘要翻译： 具有通硅通孔（TSV）的器件及其形成方法包括在硅衬底中形成开口，在开口的侧壁和底部形成第一绝缘层，形成第二绝缘体 层在开口的侧壁和底部。 第一绝缘层和硅衬底之间的第一界面具有峰 - 谷高度小于5nm的界面粗糙度。 第二绝缘层和导电层之间的第二界面具有峰 - 谷高度小于5nm的界面粗糙度。

公开(公告)号：US20100187682A1

公开(公告)日：2010-07-29

申请号：US12442192

申请日：2007-09-21

申请人： Damaruganath Pinjala ,  Navas Khan Oratti Kalandar ,  Hengyun Zhang ,  Ebin Liao ,  Qingxin Zhang ,  Nagarajan Ranganathan ,  Vaidyanathan Kripesh

发明人： Damaruganath Pinjala ,  Navas Khan Oratti Kalandar ,  Hengyun Zhang ,  Ebin Liao ,  Qingxin Zhang ,  Nagarajan Ranganathan ,  Vaidyanathan Kripesh

IPC分类号： H01L23/46 ,  H01L21/02

CPC分类号： H01L23/473 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/0652 ,  H01L2225/06589 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1627 ,  H01L2924/00 ,  H01L2224/0401

摘要： An electronic package (200) comprises a substrate (201), a first carrier layer arrangement (211) adapted to dissipate heat from at least one chip (217) mounted thereon, and a heat exchanger (221) mounted on the first carrier layer arrangement. The first carrier layer arrangement comprises at least one internal microchannel (213), which is fluidically interconnected with the heat exchanger (221) though an inlet (215) and an outlet (219). The heat exchange further comprises a pump (223) controlling fluid flow through the microchannel (213). The package may further comprise a stack of carrier layer arrangements (211), each of which may have one or more chips (217) mounted thereon.

摘要翻译： 电子封装（200）包括衬底（201），适于从安装在其上的至少一个芯片（217）散发热量的第一载体层布置（211）和安装在第一载体层布置上的热交换器（221） 。 第一载体层布置包括至少一个内部微通道（213），其通过入口（215）和出口（219）与热交换器（221）流体地互连。 热交换器还包括控制流过微通道（213）的流体的泵（223）。 该封装还可以包括一叠载体层布置（211），每个载体层布置可以具有安装在其上的一个或多个芯片（217）。

公开(公告)号：US08487410B2

公开(公告)日：2013-07-16

申请号：US13085668

申请日：2011-04-13

申请人： Chen-Hua Yu ,  Cheng-Hung Chang ,  Ebin Liao ,  Chia-Lin Yu ,  Hsiang-Yi Wang ,  Chun Hua Chang ,  Li-Hsien Huang ,  Darryl Kuo ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

发明人： Chen-Hua Yu ,  Cheng-Hung Chang ,  Ebin Liao ,  Chia-Lin Yu ,  Hsiang-Yi Wang ,  Chun Hua Chang ,  Li-Hsien Huang ,  Darryl Kuo ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC分类号： H01L29/40

CPC分类号： H01L21/76898 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/30625 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76844 ,  H01L21/76846 ,  H01L23/481 ,  H01L23/49827 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor component includes a semiconductor substrate having a top surface. An opening extends from the top surface into the semiconductor substrate. The opening includes an interior surface. A first dielectric liner having a first compressive stress is disposed on the interior surface of the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner. A metal barrier layer is disposed on the third dielectric liner. A conductive material is disposed on the metal barrier layer and fills the opening.

公开(公告)号：US20130020713A1

公开(公告)日：2013-01-24

申请号：US13497611

申请日：2009-09-25

申请人： Chirayarikathu Veedu Sankarapillai Premachandran ,  Rakesh Kumar ,  Nagarajan Ranganathan ,  Won Kyoung Choi ,  Ebin Liao ,  Yasuyuki Mitsuoka ,  Hiroshi Takahashi ,  Ryuta Mitsusue

发明人： Chirayarikathu Veedu Sankarapillai Premachandran ,  Rakesh Kumar ,  Nagarajan Ranganathan ,  Won Kyoung Choi ,  Ebin Liao ,  Yasuyuki Mitsuoka ,  Hiroshi Takahashi ,  Ryuta Mitsusue

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L21/6836 ,  B81B2207/092 ,  B81B2207/093 ,  B81B2207/097 ,  B81C2203/019 ,  H01L24/48 ,  H01L24/94 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/16195 ,  H01L2924/16235 ,  H01L2924/16315 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In an embodiment, a wafer level package may be provided. The wafer level package may include a device wafer including a MEMS device, a cap wafer disposed over the device wafer, at least one first interconnect disposed between the device wafer and the cap wafer and configured to provide an electrical connection between the device wafer and the cap wafer, and a conformal sealing ring disposed between the device wafer and the cap wafer and configured to surround the at least one first interconnect and the MEMS device so as to provide a conformally sealed environment for the at least one first interconnect and the MEMS device, wherein the conformal sealing ring may be configured to conform to a respective suitable surface of the device wafer and the cap wafer when the device wafer may be bonded to the cap wafer. A method of forming a wafer level package may also be provided.

摘要翻译： 在一个实施例中，可以提供晶片级封装。 晶片级封装可以包括包括MEMS器件的器件晶片，设置在器件晶片上的帽晶片，设置在器件晶片和帽晶片之间的至少一个第一互连，并且被配置为在器件晶片和晶片级封装之间提供电连接 帽状晶片和保形密封环，其设置在器件晶片和盖晶片之间并且被配置为围绕至少一个第一互连和MEMS器件，以便为至少一个第一互连和MEMS器件提供保形密封的环境 ，其中所述保形密封环可以被配置为当所述器件晶片可以结合到所述盖晶片时，使其符合所述器件晶片和所述盖晶片的相应合适的表面。 还可以提供一种形成晶片级封装的方法。

公开(公告)号：US20060197232A1

公开(公告)日：2006-09-07

申请号：US11361613

申请日：2006-02-24

申请人： Andrew Tay ,  Simon Ang ,  Ebin Liao

发明人： Andrew Tay ,  Simon Ang ,  Ebin Liao

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L24/72 ,  H01L24/02 ,  H01L2224/04042 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00

摘要： An interconnect structure for interconnecting an integrated circuit (IC) chip to a next level, a method of fabricating the interconnect at wafer level, and a method of interconnecting an integrated circuit (IC) chip to the next level. The interconnect structure comprises one or more planar micro-spring elements formed on a packaging surface of the chip and connected to an interconnection pad; wherein the interconnection pad is resiliently moveable horizontally and vertically with respect to the surface of the chip. A layer of solder is preferably electroplated onto the interconnection pad to provide interconnection to the next level. In a variation of the interconnect structure, a metal column is fabricated onto the interconnection pad prior to electroplating the solder layer.

摘要翻译： 用于将集成电路（IC）芯片互连到更高级别的互连结构，在晶片级制造互连的方法以及将集成电路（IC）芯片互连到下一级的方法。 互连结构包括形成在芯片的封装表面上并连接到互连焊盘的一个或多个平面微弹簧元件; 其中所述互连垫相对于所述芯片的表面水平和垂直地弹性移动。 焊料层优选地电镀在互连焊盘上以提供到下一级的互连。 在互连结构的变型中，在电镀焊料层之前，在互连焊盘上制造金属柱。

公开(公告)号：US08525343B2

公开(公告)日：2013-09-03

申请号：US12892409

申请日：2010-09-28

申请人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Ebin Liao ,  Tsang-Jiuh Wu

发明人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Ebin Liao ,  Tsang-Jiuh Wu

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L21/76831 ,  H01L21/486 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00

摘要： A device with through-silicon via (TSV) and a method of forming the same includes the formation of an opening in a silicon substrate, the formation of a first insulation layer on the sidewalls and bottom of the opening, the formation of a second insulation layer on the sidewalls and bottom of the opening. A first interface between the first insulation layer and the silicon substrate has an interface roughness with a peak-to-valley height less than 5 nm. A second interface between the second insulation layer and the conductive layer has an interface roughness with a peak-to-valley height less than 5 nm.

摘要翻译： 具有通硅通孔（TSV）的器件及其形成方法包括在硅衬底中形成开口，在开口的侧壁和底部形成第一绝缘层，形成第二绝缘体 层在开口的侧壁和底部。 第一绝缘层和硅衬底之间的第一界面具有峰 - 谷高度小于5nm的界面粗糙度。 第二绝缘层与导电层之间的第二界面具有峰 - 谷高度小于5nm的界面粗糙度。