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    Method of reducing leakage current in sub one volt SOI circuits
    31.
    发明申请
    Method of reducing leakage current in sub one volt SOI circuits 有权
    降低亚一伏SOI电路漏电流的方法

    公开(公告)号：US20050040881A1

    公开(公告)日：2005-02-24

    申请号：US10644211

    申请日：2003-08-20

    Applicant: Richard Brown ,  Ching-Te Chuang ,  Peter Cook ,  Koushik Das ,  Rajiv Joshi

    Inventor： Richard Brown ,  Ching-Te Chuang ,  Peter Cook ,  Koushik Das ,  Rajiv Joshi

    IPC: H03K19/00 ,  H03K3/01

    CPC classification number: H03K19/0016

    Abstract: A multi-threshold integrated circuit (IC) with reduced subthreshold leakage and method of reducing leakage. Selectable supply switching devices (NFETs and/or PFETS) between a logic circuit and supply connections (Vdd and Ground) for the circuit have higher thresholds than normal circuit devices. Some devices may have thresholds lowered when the supply switching devices are on. Header/footer devices with further higher threshold voltages and widths may be used to further increase off resistance and maintain/reduce on resistance. Alternatively, high threshold devices may be stacked to further reduce leakage to a point achieved for an even higher threshold. Intermediate supply connects at the devices may have decoupling capacitance and devices may be tapered for optimum stack height and an optimum taper ratio to minimize circuit leakage and circuit delay.

    Abstract translation: 具有降低的亚阈值泄漏的多阈值集成电路（IC）和减少泄漏的方法。 电路逻辑电路和电源连接（Vdd和Ground）之间的可选供电开关器件（NFET和/或PFETS）具有比正常电路器件更高的阈值。 当供电开关装置打开时，一些装置可能具有降低的阈值。 具有更高阈值电压和宽度的标题/页脚装置可用于进一步降低电阻和保持/降低电阻。 或者，可以堆叠高阈值装置以进一步将泄漏减少到达到甚至更高阈值所达到的点。 中间电源连接在器件上可能具有去耦电容，器件可以锥形化，以获得最佳堆叠高度和最佳锥度比，以最大限度地减少电路泄漏和电路延迟。

    STATIC MEMORY CELL
    32.
    发明申请
    STATIC MEMORY CELL 有权
    静态存储单元

    公开(公告)号：US20150162077A1

    公开(公告)日：2015-06-11

    申请号：US14200040

    申请日：2014-03-07

    Applicant: Ching-Te Chuang ,  Chih-Hao Chang ,  Chao-Kuei Chung ,  Chien-Yu Lu ,  Shyh-Jye Jou ,  Ming-Hsien Tu

    Inventor： Ching-Te Chuang ,  Chih-Hao Chang ,  Chao-Kuei Chung ,  Chien-Yu Lu ,  Shyh-Jye Jou ,  Ming-Hsien Tu

    IPC: G11C11/412 ,  G11C11/419

    CPC classification number: G11C11/419 ,  G11C11/412 ,  G11C11/413

    Abstract: A static memory cell is provided. The static memory cell includes a data latch circuit and a voltage provider. The data latch circuit is configured to store a bit data. The data latch circuit has a first inverter and a second inverter, and the first inverter and the second inverter are coupled to each other. The first inverter and the second inverter respectively receive a first voltage and a second voltage as power voltages. The voltage provider provides the first voltage and the second voltage to the data latch circuit. When the bit data is written to the data latch circuit, the voltage provider adjusts a voltage value of one of the first and second voltages according to the bit data.

    Abstract translation: 提供静态存储单元。 静态存储单元包括数据锁存电路和电压提供器。 数据锁存电路被配置为存储位数据。 数据锁存电路具有第一反相器和第二反相器，并且第一反相器和第二反相器彼此耦合。 第一反相器和第二反相器分别接收第一电压和第二电压作为电源电压。 电压提供器向数据锁存电路提供第一电压和第二电压。 当位数据被写入数据锁存电路时，电压提供器根据位数据调节第一和第二电压之一的电压值。

    Independently-controlled-gate SRAM
    34.
    发明授权
    Independently-controlled-gate SRAM 有权
    独立控制门SRAM

    公开(公告)号：US08717807B2

    公开(公告)日：2014-05-06

    申请号：US13419291

    申请日：2012-03-13

    Applicant: Ching-Te Chuang ,  Yin-Nien Chen ,  Chien-Yu Hsieh ,  Ming-Long Fan ,  Pi-Ho Hu ,  Pin Su

    Inventor： Ching-Te Chuang ,  Yin-Nien Chen ,  Chien-Yu Hsieh ,  Ming-Long Fan ,  Pi-Ho Hu ,  Pin Su

    IPC: G11C11/00

    CPC classification number: G11C11/412

    Abstract: The present invention provides an IG 7T FinFET SRAM, which adopts independently-controlled-gate super-high-VT FinFETs to achieve a stacking-like property, whereby to eliminate the read disturb and half-select disturb. Further, the present invention uses keeper circuits and read control voltage to reduce leakage current of the bit lines during read. Furthermore, the present invention can effectively overcome the problem of the conventional 6T SRAM that is likely to have read errors at low operation voltage.

    Abstract translation: 本发明提供了一种IG 7T FinFET SRAM，其采用独立控制的栅极超高VT FinFET来实现层叠性质，从而消除读取干扰和半选择干扰。 此外，本发明使用保持器电路和读取控制电压来减少读取期间位线的泄漏电流。 此外，本发明可以有效地克服在低操作电压下可能具有读错误的常规6T SRAM的问题。

    Single-ended SRAM with cross-point data-aware write operation
    35.
    发明授权
    Single-ended SRAM with cross-point data-aware write operation 有权
    具有跨点数据感知写操作的单端SRAM

    公开(公告)号：US08693237B2

    公开(公告)日：2014-04-08

    申请号：US13562330

    申请日：2012-07-31

    Applicant: Shyh-Jye Jou ,  Jhih-Yu Lin ,  Ching-Te Chuang ,  Ming-Hsien Tu ,  Yi-Wei Chiu

    Inventor： Shyh-Jye Jou ,  Jhih-Yu Lin ,  Ching-Te Chuang ,  Ming-Hsien Tu ,  Yi-Wei Chiu

    IPC: G11C11/00

    CPC classification number: G11C11/412

    Abstract: A single-ended SRAM including at least one memory cell and a third switch is provided. The memory cell includes a data-latching unit, a first switch, a second switch and a data-transferring unit. The data-latching unit is configured for latching the received input data and provides a storage data and the inverse data of the storage data. The first switch transfers a reference data to the data-latching unit according to a first word-line signal. The second switch transfers the reference data to the data-latching unit according to a second word-line signal. The data-transferring unit decides whether or not to transfer the reference data to the bit-line according to the storage data and a control signal. The third switch receives the reference data and the control signal and transfers the reference data to the first switch, the second switch and the data-transferring unit according to the control signal.

    Abstract translation: 提供包括至少一个存储单元和第三开关的单端SRAM。 存储单元包括数据锁存单元，第一开关，第二开关和数据传送单元。 数据锁存单元被配置为锁存接收到的输入数据，并提供存储数据和存储数据的逆数据。 第一开关根据第一字线信号将参考数据传送到数据锁存单元。 第二开关根据第二字线信号将参考数据传送到数据锁存单元。 数据传送单元根据存储数据和控制信号决定是否将参考数据传送到位线。 第三开关接收参考数据和控制信号，并根据控制信号将参考数据传送到第一开关，第二开关和数据传送单元。

    STATIC RANDOM ACCESS MEMORY APPARATUS AND BIT-LINE VOLTAGE CONTROLLER THEREOF
    36.
    发明申请
    STATIC RANDOM ACCESS MEMORY APPARATUS AND BIT-LINE VOLTAGE CONTROLLER THEREOF 有权
    静态随机存取存储器和位线电压控制器

    公开(公告)号：US20140009999A1

    公开(公告)日：2014-01-09

    申请号：US13665941

    申请日：2012-11-01

    Applicant: Ching-Te Chuang ,  Nan-Chun Lien ,  Wei-Nan Liao ,  Chi-Hsin Chang ,  Hao-I Yang ,  Wei Hwang ,  Ming-Hsien Tu

    Inventor： Ching-Te Chuang ,  Nan-Chun Lien ,  Wei-Nan Liao ,  Chi-Hsin Chang ,  Hao-I Yang ,  Wei Hwang ,  Ming-Hsien Tu

    IPC: G11C11/00

    CPC classification number: G11C11/413

    Abstract: A static random access memory apparatus and a bit-line voltage controller thereof are disclosed. The bit-line voltage controller includes a controller, a pull-up circuit, a pull-down circuit and a voltage keeping circuit. The controller receives a bank selecting signal and a clock signal, and decides a pull-up time period, a pull-down time period and a voltage keeping time period according to the bank selecting signal and the clock signal. The pull-up circuit pulls up a bit-line power according to a first reference voltage within the pull-up time period. The pull-down circuit pulls down the bit-line power according to a second reference voltage within the pull-down time period. The voltage keeping circuit keeps the bit-line power to equal to an output voltage during the voltage keeping time period. The voltage keeping time period is after the pull-up time period and the pull-down time period.

    Abstract translation: 公开了一种静态随机存取存储器及其位线电压控制器。 位线电压控制器包括控制器，上拉电路，下拉电路和保压电路。 控制器接收存储体选择信号和时钟信号，并且根据存储体选择信号和时钟信号确定上拉时间段，下拉时间段和保持时间周期。 上拉电路在上拉时间段内根据第一个参考电压拉出位线电源。 下拉电路在下拉时间段内根据第二参考电压拉低位线电源。 电压保持电路在电压保持时间段期间将位线功率保持为等于输出电压。 电压保持时间段在上拉时间段和下拉时间段之后。

    THRESHOLD VOLTAGE MEASUREMENT DEVICE
    37.
    发明申请
    THRESHOLD VOLTAGE MEASUREMENT DEVICE 有权
    阈值电压测量装置

    公开(公告)号：US20130301343A1

    公开(公告)日：2013-11-14

    申请号：US13597733

    申请日：2012-08-29

    Applicant: Ching-Te Chuang ,  Shyh-Jye Jou ,  Geng-Cing Lin ,  Shao-Cheng Wang ,  Yi-Wei Lin ,  Ming-Chien Tsai ,  Wei-Chiang Shih ,  Nan-Chun Lien ,  Kuen-Di Lee ,  Jyun-Kai Chu

    Inventor： Ching-Te Chuang ,  Shyh-Jye Jou ,  Geng-Cing Lin ,  Shao-Cheng Wang ,  Yi-Wei Lin ,  Ming-Chien Tsai ,  Wei-Chiang Shih ,  Nan-Chun Lien ,  Kuen-Di Lee ,  Jyun-Kai Chu

    IPC: G11C11/40

    CPC classification number: G11C29/50004 ,  G11C11/41 ,  G11C29/12005

    Abstract: A threshold voltage measurement device is disclosed. The device is coupled to a 6T SRAM. The SRAM comprises two inverters each coupled to a FET. Power terminals of one inverter are in a floating state; the drain and source of the FET coupled to the inverter are short-circuited. Two voltage selectors, a resistor, an amplifier and the SRAM are connected in a negative feedback way. Different bias voltages are applied to the SRAM for measuring threshold voltages of two FETs of the other inverter and the FET coupled to the other inverter. The present invention uses a single circuit to measure the threshold voltages of the three FETs without changing the physical structure of the SRAM. Thereby is accelerated the measurement and decreased the cost of the fabrication process and measurement instruments.

    Abstract translation: 公开了一种阈值电压测量装置。 该器件耦合到6T SRAM。 SRAM包括两个各自耦合到FET的反相器。 一个逆变器的电源端子处于浮动状态; 耦合到逆变器的FET的漏极和源极短路。 两个电压选择器，电阻，放大器和SRAM以负反馈的方式连接。 不同的偏置电压被施加到SRAM，用于测量另一个反相器的两个FET和耦合到另一个反相器的FET的阈值电压。 本发明使用单个电路来测量三个FET的阈值电压，而不改变SRAM的物理结构。 从而加快了测量并降低了制造过程和测量仪器的成本。

    Disturb-free static random access memory cell
    39.
    发明授权
    Disturb-free static random access memory cell 有权
    无噪音静态随机存取存储单元

    公开(公告)号：US08259510B2

    公开(公告)日：2012-09-04

    申请号：US12772238

    申请日：2010-05-03

    Applicant: Ching-Te Chuang ,  Hao-I Yang ,  Jihi-Yu Lin ,  Shyh-Chyi Yang ,  Ming-Hsien Tu ,  Wei Hwang ,  Shyh-Jye Jou ,  Kun-Ti Lee ,  Hung-Yu Li

    Inventor： Ching-Te Chuang ,  Hao-I Yang ,  Jihi-Yu Lin ,  Shyh-Chyi Yang ,  Ming-Hsien Tu ,  Wei Hwang ,  Shyh-Jye Jou ,  Kun-Ti Lee ,  Hung-Yu Li

    IPC: G11C7/00

    CPC classification number: G11C11/412

    Abstract: A disturb-free static random access memory cell includes: a latch circuit having a first access terminal and a second access terminal; a first switching circuit having a first bit transferring terminal coupled to the first access terminal, a first control terminal coupled to a first write word line, and a second bit transferring terminal; a second switching circuit having a third bit transferring terminal coupled to the second access terminal, a second control terminal coupled to a second write word line, and a fourth bit transferring terminal coupled to the second bit transferring terminal; a third switching circuit having a fifth bit transferring terminal coupled to the fourth bit transferring terminal, a third control terminal coupled to a word line, and a sixth bit transferring terminal coupled to a bit line; and a sensing amplifier coupled to the bit line, for determining a bit value appearing at the bit line.

    Abstract translation: 无干扰的静态随机存取存储单元包括：具有第一接入终端和第二接入终端的锁存电路; 第一切换电路，具有耦合到第一接入终端的第一比特传送终端，耦合到第一写字线的第一控制终端和第二比特传送终端; 第二切换电路，具有耦合到第二接入终端的第三比特传送终端，耦合到第二写字线的第二控制终端，以及耦合到第二比特传送终端的第四比特传送终端。 第三开关电路，具有耦合到第四位转移终端的第五位转移终端，耦合到字线的第三控制端和耦合到位线的第六位转移端; 以及耦合到位线的感测放大器，用于确定出现在位线处的位值。

    ASYMMETRIC VIRTUAL-GROUND SINGLE-ENDED SRAM AND SYSTEM THEREOF
    40.
    发明申请
    ASYMMETRIC VIRTUAL-GROUND SINGLE-ENDED SRAM AND SYSTEM THEREOF 审中-公开
    不对称虚拟地面单端SRAM及其系统

    公开(公告)号：US20120057399A1

    公开(公告)日：2012-03-08

    申请号：US12876682

    申请日：2010-09-07

    Applicant: Shyh-Jye JOU ,  Jhih-Yu Lin ,  Ching-Te Chuang ,  Ming-Hsien Tu ,  Ming-Chien Tsai

    Inventor： Shyh-Jye JOU ,  Jhih-Yu Lin ,  Ching-Te Chuang ,  Ming-Hsien Tu ,  Ming-Chien Tsai

    IPC: G11C11/00

    CPC classification number: G11C11/413

    Abstract: The present invention discloses an asymmetric virtual-ground single-ended SRAM and a system thereof, wherein a first inverter is coupled to a high potential and a virtual ground, and wherein the first inverter and a second inverter form a latch loop, and wherein a third inverter is electrically connected with the second inverter, and wherein the third inverter and the second inverter are jointly coupled to the high potential and a ground. A write word line and a read word line control an access transistor and a pass transistor to undertake writing and reading of signals. A plurality of asymmetric virtual-ground single-ended SRAMs forms a memory system.

    Abstract translation: 本发明公开了一种非对称虚拟地单端SRAM及其系统，其中第一反相器耦合到高电位和虚拟地，并且其中第一反相器和第二反相器形成锁存环，并且其中 第三反相器与第二反相器电连接，并且其中第三反相器和第二反相器共同耦合到高电位和接地。 写字线和读字线控制存取晶体管和传输晶体管以进行信号的写入和读取。 多个非对称虚拟地单端SRAM形成存储器系统。

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