公开(公告)号：US07861044B2

公开(公告)日：2010-12-28

申请号：US11945311

申请日：2007-11-27

Applicant: Wen-Juin Huang ,  Chung-Ching Huang ,  Chien-Ping Chung

Inventor： Wen-Juin Huang ,  Chung-Ching Huang ,  Chien-Ping Chung

IPC: G06F13/00 ,  G06F13/28 ,  G06F13/14

CPC classification number: G06F12/1416 ,  G06F9/30003 ,  G06F2212/2022

Abstract: A memory access method for accessing data from a non-volatile memory in a south bridge is provided. Memory access is performed under a system management mode (SMM). Under the protection of the SMM mode, the desired memory address is not altered by an interrupt handler, therefore memory data is accessed correctly.

Abstract translation: 提供了一种用于从南桥的非易失性存储器访问数据的存储器访问方法。 在系统管理模式（SMM）下执行内存访问。 在SMM模式的保护下，所需的存储器地址不会被中断处理程序改变，因此存储器数据被正确访问。

公开(公告)号：US07802119B2

公开(公告)日：2010-09-21

申请号：US11707966

申请日：2007-02-20

Applicant: Wen-Juin Huang ,  Chung-Ching Huang ,  Jui-Ming Wei

Inventor： Wen-Juin Huang ,  Chung-Ching Huang ,  Jui-Ming Wei

IPC: G06F1/00 ,  G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/3243 ,  Y02D10/152

Abstract: For saving power of a central processing unit at a C3 power level upon processing a bus master request from a peripheral device, an arbitrator is disabled from transmitting any request to the central processing unit at the C3 power level. Afterwards, in response to a bus master request, the central processing unit is switched from the C3power level to a transitional C0 power level while keeping the arbitrator disabled, and then switched from the transitional C0 power level to a C2 power level while enabling the arbitrator to process the bus master request.

Abstract translation: 为了在从外围设备处理总线主机请求时以C3功率电平节省中央处理单元的功率，仲裁器被禁止在C3功率电平向中央处理单元发送任何请求。 之后，响应于总线主机请求，中央处理单元从C3power电平切换到过渡C0功率电平，同时保持仲裁器禁用，然后从过渡C0功率电平切换到C2功率电平，同时启用仲裁器 处理总线主机请求。

公开(公告)号：US07363408B2

公开(公告)日：2008-04-22

申请号：US11000300

申请日：2004-11-30

Applicant: Tony Ho ,  Chung-Ching Huang ,  Norman Chung

Inventor： Tony Ho ,  Chung-Ching Huang ,  Norman Chung

IPC: G06F13/24

CPC classification number: G06F13/24 ,  Y02D10/14

Abstract: An interruption control system includes an interruption message generator, a stop clock control module and an interruption status indicating path. The interruption message generator is used for decoding and identifying a message signaled interrupt (MSI) issued by a first peripheral device or a second peripheral device when interruption is to be conducted, and generates an interruption status indicating message in response to the message signaled interrupt (MSI). The stop clock control module is coupled to the interruption message generator and the CPU and de-asserts a stop clock signal that is previously asserted to have the CPU enter a power-saving state to have the CPU deactivate the power-saving state in response to the interruption status indicating message. The interruption status indicating path is used for transmitting the interruption status indicating message.

Abstract translation: 中断控制系统包括中断消息发生器，停止时钟控制模块和中断状态指示路径。 所述中断消息发生器用于在进行中断时解码和识别由第一外围设备或第二外围设备发出的消息信号中断（MSI），并响应于消息信号中断产生中断状态指示消息（ MSI）。 停止时钟控制模块耦合到中断消息发生器和CPU，并且取消断言先前断言的停止时钟信号，以使CPU进入省电状态，以使CPU能够响应于CPU 中断状态指示消息。 中断状态指示路径用于发送中断状态指示消息。

公开(公告)号：US20080012585A1

公开(公告)日：2008-01-17

申请号：US11622027

申请日：2007-01-11

Applicant: Chien-Ping Chung ,  Chung-Ching Huang

Inventor： Chien-Ping Chung ,  Chung-Ching Huang

IPC: G01R27/08

CPC classification number: G06F1/324 ,  G06F1/3228 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: Apparatus and methods of adjusting system efficiency for a current-consuming system are disclosed. In the disclosed apparatus, a system current detector receives a system current from the current-consuming system and calculates a system current variation accordingly. A system efficiency adjustment module is coupled to the system current detector to receive the system current variation and output a frequency control signal and a voltage control signal accordingly.

Abstract translation: 公开了一种调节耗电系统效率的装置和方法。 在所公开的装置中，系统电流检测器从耗电系统接收系统电流并相应地计算系统电流变化。 系统效率调节模块耦合到系统电流检测器以接收系统电流变化并相应地输出频率控制信号和电压控制信号。

公开(公告)号：US20070162772A1

公开(公告)日：2007-07-12

申请号：US11409974

申请日：2006-04-25

Applicant: Wen Huang ,  Chung-Ching Huang ,  Hao Lin ,  Yeh Cho

Inventor： Wen Huang ,  Chung-Ching Huang ,  Hao Lin ,  Yeh Cho

IPC: G06F1/00

CPC classification number: G06F1/3203

Abstract: A power saving method and system thereof is disclosed. When the central processing unit is under a non-snooping sleep state and a peripheral device sends a bus master request, a chip will drive the central processing unit waking from the non-snooping sleep state and entering a system management mode for executing an interrupt service routine that makes the central processing unit in halt status. The central processing unit is then driven to enter a snooping sleep state for snooping the bus master request. After the execution of the bus master request, the chip will drive the central processing unit to leave the snooping sleep state and return to the non-snooping sleep state for power consumption conservation.

Abstract translation: 公开了一种省电方法及其系统。 当中央处理单元处于非窥探睡眠状态并且外围设备发送总线主机请求时，芯片将驱动中央处理单元从非窥探睡眠状态唤醒并进入用于执行中断服务的系统管理模式 使中央处理单元处于停止状态的程序。 然后中央处理单元被驱动以进入窥探睡眠状态以窥探总线主控请求。 执行总线主机请求后，芯片将驱动中央处理单元离开窥探睡眠状态，并返回到非窥探睡眠状态，以实现功耗节省。

公开(公告)号：US20070157039A1

公开(公告)日：2007-07-05

申请号：US11505973

申请日：2006-08-18

Applicant: Wen-Juin Huang ,  Chung-Ching Huang

Inventor： Wen-Juin Huang ,  Chung-Ching Huang

IPC: G06F1/00

CPC classification number: G06F1/3228

Abstract: A power saving method applied to a central processing unit under a non-snooping sleeping state with a bus master request from a peripheral device is presented. In accordance with the present invention, first prohibit the central processing unit from fetching instruction. Then drive the central processing unit entering a snooping sleeping state and enabling the arbiter for transferring the bus master request to the central processing unit. After the central processing unit completes the bus master request, the arbiter is disabled and the central processing unit is driven to leave the snooping sleeping state and return back to the non-snooping sleeping state. Therefore, the power consumed by the central processing unit is reduced so as to save power.

Abstract translation: 提出了一种在具有来自外围设备的总线主机请求的非窥探睡眠状态下应用于中央处理单元的省电方法。 根据本发明，首先禁止中央处理单元取出指令。 然后驱动中央处理单元进入窥探睡眠状态，并允许仲裁器将总线主控请求传送到中央处理单元。 中央处理单元完成总线主机请求后，仲裁器被禁止，中央处理单元被驱动离开窥探休眠状态并返回到非窥探睡眠状态。 因此，中央处理单元消耗的功率降低，从而节省功率。

公开(公告)号：US07206883B2

公开(公告)日：2007-04-17

申请号：US10945000

申请日：2004-09-20

Applicant: Tony Ho ,  Chung-Ching Huang ,  Norman Chung

Inventor： Tony Ho ,  Chung-Ching Huang ,  Norman Chung

IPC: G06F13/24 ,  G06F13/36 ,  G06F1/00

CPC classification number: G06F13/24 ,  G06F13/4027 ,  G06F2213/0024 ,  Y02D10/14 ,  Y02D10/151

Abstract: An interruption control system includes a first input/output interruption controller, a second input/output interruption controller, and an interruption control device bus. The first input/output interruption controller is coupled to a first peripheral device and a south bridge chip, and asserts a wake-up signal to the south bridge chip in response to a first interrupt signal issued by the first peripheral device so as to deactivate a power-saving state of the computer system. The second input/output interruption controller is coupled to a second peripheral device and a north bridge chip, and asserts a third interrupt signal in response to a second interrupt signal issued by the second peripheral device. Via the interruption control device bus, the third interrupt signal is transmitted from the second input/output interruption controller to the first input/output interruption controller, wherein the first input/output interruption controller asserts the wake-up signal to deactivate the power-saving state of the computer system in response to the third interrupt signal.

Abstract translation: 中断控制系统包括第一输入/输出中断控制器，第二输入/输出中断控制器和中断控制设备总线。 第一输入/输出中断控制器耦合到第一外围设备和南桥芯片，并且响应于由第一外围设备发出的第一中断信号而向南桥芯片发出唤醒信号，以便使第 计算机系统的省电状态。 第二输入/输出中断控制器耦合到第二外围设备和北桥芯片，并且响应于由第二外围设备发出的第二中断信号而断言第三中断信号。 通过中断控制装置总线，第三中断信号从第二输入/输出中断控制器发送到第一输入/输出中断控制器，其中第一输入/输出中断控制器断言唤醒信号以去激活省电 计算机系统的状态响应于第三中断信号。

公开(公告)号：US20050154803A1

公开(公告)日：2005-07-14

申请号：US11009881

申请日：2004-12-10

Applicant: Chung-Ching Huang ,  Lin-Hung Chen ,  Hao-Lin Lin

Inventor： Chung-Ching Huang ,  Lin-Hung Chen ,  Hao-Lin Lin

IPC: G06F12/00 ,  G06F13/10 ,  G06F13/28

CPC classification number: G06F13/102

Abstract: A method for accessing a memory of a computer system for BIOS codes optionally performs a detection procedure to realize a maximum memory burst read size of the memory according to a flag value upon the computer system is initialized. For example, the detection procedure is performed when the flag value is logic “1” and the detection procedure is not performed when the flag value is logic “0”. When the detection procedure is performed, read requests with sequentially reduced memory burst read sizes are asserted to the memory one by one until the maximum memory burst read size of the memory is realized. Then, the BIOS codes are read from the memory with the maximum memory burst read size.

Abstract translation: 用于访问用于BIOS代码的计算机系统的存储器的方法可选地执行检测过程，以在计算机系统初始化时根据标志值实现存储器的最大存储器突发读取大小。 例如，当标志值为逻辑“1”时执行检测过程，并且当标志值为逻辑“0”时不执行检测过程。 当执行检测过程时，依次减少的存储器突发读取大小的读取请求被逐个断言给存储器，直到实现存储器的最大存储器突发读取大小。 然后，从具有最大存储突发读取大小的存储器中读取BIOS代码。

公开(公告)号：US20050086459A1

公开(公告)日：2005-04-21

申请号：US10965405

申请日：2004-10-14

Applicant: Yeh Cho ,  Chung-Ching Huang

Inventor： Yeh Cho ,  Chung-Ching Huang

IPC: G06F3/06 ,  G06F9/00 ,  G06F9/44 ,  G06F9/445

CPC classification number: G06F3/0632 ,  G06F3/0607 ,  G06F3/0676 ,  G06F9/4411

Abstract: A method and apparatus for driving a non-native SATA hard disk applied in a computer is provided. The computer includes a basic input/output system (BIOS) and an operating system (OS), both of which support an advanced configuration and power interface (ACPI). The non-native SATA hard disk includes a conversion interface and a parallel ATA (PATA) internal disk. First, issue an interrupt. Then, process an interrupt handle routine for detecting and saving the timing mode of the PATA internal disk. Next, load a default IDE driver. Then, report the saved timing mode. Finally, set the SATA hard disk according to the timing mode.

Abstract translation: 提供了一种用于驱动应用在计算机中的非本机SATA硬盘的方法和装置。 该计算机包括基本的输入/输出系统（BIOS）和操作系统（OS），两者都支持高级配置和电源接口（ACPI）。 非本机SATA硬盘包括转换接口和并行ATA（PATA）内部磁盘。 首先发出中断。 然后处理一个中断处理程序，用于检测和保存PATA内部磁盘的定时模式。 接下来，加载默认的IDE驱动程序。 然后，报告保存的定时模式。 最后，根据定时模式设置SATA硬盘。

公开(公告)号：US20050060617A1

公开(公告)日：2005-03-17

申请号：US10820768

申请日：2004-04-09

Applicant: Chung-Ching Huang ,  Hao-Lin Lin

Inventor： Chung-Ching Huang ,  Hao-Lin Lin

IPC: G06F11/00

CPC classification number: G06F11/362

Abstract: A debugging device and method are provided, including a central processing unit (CPU) connected to a chipset with a system management interrupt pin. The debugging method includes sending out a system management interrupt signal to central processing unit from the system management interrupt pin of the chipset. Then the CPU moves into a system management mode and pops out a debugging operation window for selecting and executing each debugging item. After the execution of each debugging item is completed, the CPU will leave the debugging operation window and return to the next instruction before debugging. After the execution of each debugging item is completed in the debugging operation window, the CPU will return to the operation system and continue the execution of next instruction before debugging. The execution of debugging will not influence the status and the program execution from the operating system. The disclosed debugging method is convenient for executing each debugging item at any time.

Abstract translation: 提供了一种调试设备和方法，包括连接到具有系统管理中断引脚的芯片组的中央处理单元（CPU）。 调试方法包括从芯片组的系统管理中断引脚向中央处理单元发送系统管理中断信号。 然后CPU进入系统管理模式，并弹出一个调试操作窗口，用于选择和执行每个调试项目。 每个调试项目的执行完成后，CPU将离开调试操作窗口，并在调试前返回到下一条指令。 在调试操作窗口中完成每个调试项目的执行后，CPU将返回到操作系统，并在调试之前继续执行下一条指令。 调试的执行不会影响操作系统的状态和程序的执行。 所公开的调试方法可以随时执行每个调试项目。