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    Methods of Forming Fine Patterns In Integrated Circuits Using Atomic Layer Deposition
    31.
    发明申请
    Methods of Forming Fine Patterns In Integrated Circuits Using Atomic Layer Deposition 审中-公开
    在使用原子层沉积的集成电路中形成精细图案的方法

    公开(公告)号：US20080076070A1

    公开(公告)日：2008-03-27

    申请号：US11554324

    申请日：2006-10-30

    Applicant: Cha-won Koh ,  Han-ku Cho ,  Gi-sung Yeo ,  Yool Kang ,  Ji-young Lee ,  Doo-youl Lee

    Inventor： Cha-won Koh ,  Han-ku Cho ,  Gi-sung Yeo ,  Yool Kang ,  Ji-young Lee ,  Doo-youl Lee

    IPC: G03F7/00

    CPC classification number: H01L21/31144 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76816

    Abstract: A fine pattern is formed in an integrated circuit substrate, by forming a sacrificial pattern on the integrated circuit substrate. The sacrificial pattern includes tops and side walls. Atomic layer deposition is then performed to atomic layer deposit a mask material layer on the sacrificial pattern, including on the tops and the side walls thereof, and on the integrated circuit substrate therebetween. The mask material layer that was atomic layer deposited is then etched, to expose the top and the integrated circuit therebetween, such that a mask material pattern remains on the side walls. The sacrificial pattern is then removed, and the integrated circuit substrate is then etched through the mask material pattern that remains.

    Abstract translation: 通过在集成电路基板上形成牺牲图案，在集成电路基板上形成精细图案。 牺牲图案包括顶部和侧壁。 然后进行原子层沉积以在牺牲图案上沉积掩模材料层，包括在其顶部和侧壁上以及其间的集成电路基板上。 然后蚀刻原子层沉积的掩模材料层，以暴露其间的顶部和集成电路，使得掩模材料图案残留在侧壁上。 然后去除牺牲图案，然后通过保留的掩模材料图案蚀刻集成电路基板。

    Thin film type solar cell and fabrication method thereof
    33.
    发明授权
    Thin film type solar cell and fabrication method thereof 有权
    薄膜型太阳能电池及其制造方法

    公开(公告)号：US09312405B2

    公开(公告)日：2016-04-12

    申请号：US13560951

    申请日：2012-07-27

    Applicant: Sung-Chul Lee ,  Doo-Youl Lee ,  Young-Jin Kim ,  Young-Su Kim ,  Young-Soo Kim ,  Dong-Hun Lee

    Inventor： Sung-Chul Lee ,  Doo-Youl Lee ,  Young-Jin Kim ,  Young-Su Kim ,  Young-Soo Kim ,  Dong-Hun Lee

    IPC: H01L21/00 ,  H01L31/0224 ,  H01L31/068 ,  H01L31/18

    CPC classification number: H01L31/065 ,  H01L31/02168 ,  H01L31/022441 ,  H01L31/0682 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

    Abstract: A method of fabricating a solar cell includes forming a doped portion having a first conductive type on a semiconductor substrate, growing an oxide layer on the semiconductor substrate, forming a plurality of recess portions in the oxide layer, further growing the oxide layer on the semiconductor substrate, forming a doped portion having a second conductive type on areas of the semiconductor substrate corresponding to the recess portions, forming a first conductive electrode electrically coupled to the doped portion having the first conductive type, and forming a second conductive electrode on the semiconductor substrate and electrically coupled to the doped portion having the second conductive type, wherein a gap between the doped portions having the first and second conductive types corresponds to a width of the oxide layer formed by further growing the oxide layer.

    Abstract translation: 一种制造太阳能电池的方法包括在半导体衬底上形成具有第一导电类型的掺杂部分，在半导体衬底上生长氧化物层，在氧化物层中形成多个凹陷部分，在半导体上进一步生长氧化物层 在所述半导体衬底的与所述凹部对应的区域上形成具有第二导电类型的掺杂部分，形成与所述第一导电类型的所述掺杂部分电耦合的第一导电电极，以及在所述半导体衬底上形成第二导电电极 并且电耦合到具有第二导电类型的掺杂部分，其中具有第一和第二导电类型的掺杂部分之间的间隙对应于通过进一步生长氧化物层形成的氧化物层的宽度。

    Photoelectric device
    34.
    发明授权
    Photoelectric device 有权
    光电器件

    公开(公告)号：US08889981B2

    公开(公告)日：2014-11-18

    申请号：US13424450

    申请日：2012-03-20

    Applicant: Doo-Youl Lee ,  Young-Jin Kim ,  Dong-Seop Kim ,  Chan-Bin Mo ,  Young-Su Kim ,  Young-Sang Park

    Inventor： Doo-Youl Lee ,  Young-Jin Kim ,  Dong-Seop Kim ,  Chan-Bin Mo ,  Young-Su Kim ,  Young-Sang Park

    IPC: H01L31/00 ,  H01L31/0224 ,  H01L31/0352 ,  H01L31/075 ,  H01L31/0747

    CPC classification number: H01L31/022441 ,  H01L31/0352 ,  H01L31/0745 ,  H01L31/0747 ,  H01L31/075 ,  Y02E10/547 ,  Y02E10/548

    Abstract: A photoelectric device includes a first semiconductor structure and a second semiconductor structure on a substrate, and the first semiconductor structure includes a different conductivity type from the second semiconductor structure. The photoelectric device also includes a first electrode on the first semiconductor structure and a second electrode on the second semiconductor structure, and an interlayer insulating structure adjacent to the second semiconductor structure. The interlayer insulating structure separates the first semiconductor structure from the second semiconductor structure and separates the first semiconductor structure from the second electrode.

    Abstract translation: 光电器件在衬底上包括第一半导体结构和第二半导体结构，并且第一半导体结构包括与第二半导体结构不同的导电类型。 光电器件还包括第一半导体结构上的第一电极和第二半导体结构上的第二电极以及与第二半导体结构相邻的层间绝缘结构。 层间绝缘结构将第一半导体结构与第二半导体结构分开，并将第一半导体结构与第二电极分离。

    PHOTOVOLTAIC DEVICE
    35.
    发明申请
    PHOTOVOLTAIC DEVICE 审中-公开
    光电器件

    公开(公告)号：US20130087192A1

    公开(公告)日：2013-04-11

    申请号：US13445851

    申请日：2012-04-12

    Applicant: Young-Su Kim ,  Doo-Youl Lee ,  Young-Jin Kim ,  Chan-Bin Mo ,  Young-Sang Park

    Inventor： Young-Su Kim ,  Doo-Youl Lee ,  Young-Jin Kim ,  Chan-Bin Mo ,  Young-Sang Park

    IPC: H01L31/0224 ,  H01L31/18

    CPC classification number: H01L31/022441 ,  Y02E10/547

    Abstract: A photovoltaic device, and a method of fabricating the same are provided. Here, a base portion and an emitter portion are formed on a surface of a semiconductor substrate. An insulation layer is formed on the base portion and the emitter portion. The insulation layer has a plurality of vias to partially expose the base portion and the emitter portion. A first electrode is formed to contact a region of the emitter portion through at least one of the vias, and a second electrode is formed to contact a region of the base portion through at least another one of the vias. Then, a dicing line is set at a bus electrode portion of the second electrode, and the semiconductor substrate is split into at least two photovoltaic devices at the base portion along the dicing line.

    Abstract translation: 提供一种光电器件及其制造方法。 这里，在半导体衬底的表面上形成基极部分和发射极部分。 绝缘层形成在基部和发射极部分上。 绝缘层具有多个通孔以部分地暴露基部和发射极部分。 第一电极形成为通过至少一个通孔接触发射极部分的区域，并且第二电极形成为通过至少另一个通孔接触基部的区域。 然后，将切割线设置在第二电极的总线电极部分，并且半导体衬底沿着切割线在基部分割成至少两个光伏器件。

    METHOD OF FORMING FINE PATTERNS OF SEMICONDUCTOR DEVICE
    38.
    发明申请
    METHOD OF FORMING FINE PATTERNS OF SEMICONDUCTOR DEVICE 失效
    形成半导体器件精细图案的方法

    公开(公告)号：US20080206686A1

    公开(公告)日：2008-08-28

    申请号：US11781987

    申请日：2007-07-24

    Applicant: Doo-youl LEE ,  Han-ku CHO ,  Suk-joo LEE ,  Gi-sung YEO ,  Pan-suk KWAK ,  Min-jong HONG

    Inventor： Doo-youl LEE ,  Han-ku CHO ,  Suk-joo LEE ,  Gi-sung YEO ,  Pan-suk KWAK ,  Min-jong HONG

    IPC: G03C5/00

    CPC classification number: H01L21/0337

    Abstract: A method of forming fine patterns on a semiconductor substrate includes forming a first pattern, including first line patterns having a feature size F and an arbitrary pitch P, and forming a second pattern, including second line patterns disposed between adjacent first line patterns, to form a fine pattern having a half pitch P/2, the first and second line patterns being repeated in the first direction. A gap is formed in at least one first line pattern in a second direction, perpendicular to the first direction, to connect second line patterns positioned on each side of the first line pattern through the gap. At least one jog pattern, extending in the first direction, is formed from at least one first line pattern adjacent to the connected second line patterns. The jog pattern causes a gap in at least one of the connected second line patterns in the second direction.

    Abstract translation: 在半导体衬底上形成精细图案的方法包括形成包括具有特征尺寸F和任意间距P的第一线图案的第一图案，以及形成包括布置在相邻第一线图案之间的第二线图案的第二图案，以形成 具有半间距P / 2的精细图案，第一和第二线图案沿第一方向重复。 在与第一方向垂直的第二方向上的至少一个第一线图案中形成间隙，以通过间隙连接位于第一线图案的每一侧上的第二线图案。 至少一个沿着第一方向延伸的点动图案由与连接的第二线图案相邻的至少一个第一线图案形成。 所述点动图案在所述第二方向上在所连接的第二线图案中的至少一个中形成间隙。

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