公开(公告)号：US20170286793A1

公开(公告)日：2017-10-05

申请号：US15183817

申请日：2016-06-16

Applicant: Faraday Technology Corp.

Inventor： Chien-Chung Tseng

IPC: G06K9/32 ,  G06K9/40 ,  G06K9/38 ,  G06K9/46 ,  G06K9/48

CPC classification number: G06K9/325 ,  G06K9/38 ,  G06K9/40 ,  G06K9/4604 ,  G06K9/4638 ,  G06K9/4661 ,  G06K9/48 ,  G06K2009/485 ,  G06K2209/15

Abstract: A method for performing registration plate detection includes: performing image processing on image data of a predetermined region in an image to generate an edge image; and performing registration plate detection according to the edge image and the image data of the predetermined region to determine a location of a registration plate image within the predetermined region, for performing a post-processing corresponding to the registration plate image. The step of performing the image processing includes: performing gradient calculations on image data of the predetermined region to generate a gradient image, where the gradient image includes gradient data of the predetermined region; performing edge threshold estimation on the gradient data of the predetermined region, to update an edge threshold through a set of iterative calculations; and generating the edge image according to the edge threshold and according to selective gradient data of the predetermined region.

公开(公告)号：US20170126212A1

公开(公告)日：2017-05-04

申请号：US15046451

申请日：2016-02-18

Applicant: Faraday Technology Corp.

Inventor： Chiang-Hsiang Liao ,  Sheng-Hua Chen

IPC: H03K3/037

CPC classification number: H03K3/0375 ,  H03K3/0372 ,  H03K3/3562

Abstract: A flip-flop circuit including a first logic circuit, a first master latch, a second master latch, and a slave latch is provided. The first logic circuit operates a logic operation on a selecting signal and a clock signal to generate a first control signal. The first master latch receives a data signal according to the first control signal and latches the data signal according to the selecting signal and the clock signal. The second master latch receives a scan data signal according to the selecting signal and the clock signal, wherein an output terminal of the second master latch is directly connected to an output terminal of the first master latch. The slave latch latches a signal on the output terminals of the first and second master latches for generating an output signal.

公开(公告)号：US09537449B1

公开(公告)日：2017-01-03

申请号：US14856571

申请日：2015-09-17

Applicant: Faraday Technology Corp.

Inventor： Wei-Chieh Liao ,  Chi-Sheng Liao

IPC: H03B5/36 ,  G06F17/50

CPC classification number: H03B5/364 ,  G06F17/5036 ,  G06F17/5063

Abstract: A crystal oscillation circuit, a gain stage of the crystal oscillation circuit and a method for designing the same are provided. The gain stage includes multiple amplifiers and multiple current-limiting resistors. Input terminals of the amplifiers are coupled together to a first bonding pad, wherein transconductances of the amplifiers are different from each other. The first bonding pad is used for electrically coupling to a first terminal of an oscillation crystal module. First terminals of the current-limiting resistors are respectively coupled to output terminals of the amplifiers in a one-on-one manner, and second terminals of the current-limiting resistors are coupled together to a second bonding pad, wherein the second bonding pad is used for electrically coupling to a second terminal of the oscillation crystal module.

Abstract translation: 提供晶体振荡电路，晶体振荡电路的增益级及其设计方法。 增益级包括多个放大器和多个限流电阻。 放大器的输入端子耦合到第一接合焊盘，其中放大器的跨导彼此不同。 第一焊盘用于电耦合到振荡晶体模块的第一端子。 限流电阻器的第一端子分别以一对一的方式耦合到放大器的输出端子，并且限流电阻器的第二端子耦合到第二焊盘，其中第二焊盘是 用于电耦合到振荡晶体模块的第二端子。

公开(公告)号：US09484085B1

公开(公告)日：2016-11-01

申请号：US15098329

申请日：2016-04-14

Applicant: Faraday Technology Corporation ,  Faraday Technology Corp.

Inventor： Zhao-Yong Zhang ,  Kun-Ti Lee

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C11/412

Abstract: A static memory apparatus and a static memory cell thereof are provided. The static memory cell includes a data latch circuit, a data write-in circuit and a data read-out circuit. The data latch circuit has a first tristate output inverting circuit and a second tristate output inverting circuit. The data write-in circuit provides a first reference voltage to a power receiving terminal of a selected tristate output inverting circuit which is one of the first and second tristate output inverting circuits, and provides a second reference voltage to an input terminal of the selected tristate output inverting circuit during a data write-in time period. The data read-out circuit generates read-out data according to a voltage at an output terminal of the second tristate output inverting circuit and the second reference voltage during a data read-out time period.

Abstract translation: 提供了一种静态存储装置及其静态存储单元。 静态存储单元包括数据锁存电路，数据写入电路和数据读出电路。 数据锁存电路具有第一三态输出反相电路和第二三态输出反相电路。 数据写入电路向作为第一和第二三态输出反相电路之一的所选三态输出反相电路的功率接收端提供第一参考电压，并向所选三态输入端的输入端提供第二参考电压 在数据写入期间输出反相电路。 数据读出电路根据数据读出期间的第二三态输出反相电路的输出端的电压和第二基准电压来生成读出数据。

公开(公告)号：US11736108B2

公开(公告)日：2023-08-22

申请号：US17974532

申请日：2022-10-27

Applicant: Faraday Technology Corp.

Inventor： Ko-Ching Chao ,  Chih-Hung Wu ,  Po-Wen Hsiao ,  Zhou-Lun Liou

IPC: H03L7/00 ,  G11C11/4076 ,  H03K21/02 ,  H03K19/21

CPC classification number: H03L7/00 ,  G11C11/4076 ,  H03K19/21 ,  H03K21/023

Abstract: A method for performing divided-clock phase synchronization in a multi-divided-clock system, an associated synchronization control circuit, an associated synchronization control sub-circuit and an associated electronic device are provided. The method may include: performing frequency division operations according to a source clock to generate a first divided clock and a second divided clock; performing phase relationship detection on the first divided clock according to the second divided clock to generate a phase relationship detection result signal; performing a logic operation on a first phase selection result output signal and the phase relationship detection result signal to generate a second phase selection result output signal; and outputting one of the second divided clock and an inverted signal of the second divided clock according to the second phase selection result output signal, for further use in a physical layer circuit.

公开(公告)号：US20230029065A1

公开(公告)日：2023-01-26

申请号：US17542531

申请日：2021-12-06

Applicant: Faraday Technology Corporation ,  Faraday Technology Corp.

Inventor： Bu-Qing Ping

IPC: G06F13/42 ,  H04L69/324

Abstract: The invention provides a transaction layer circuit of a PCIe. The transaction layer circuit includes transaction layer processing channels, a channel selection circuit, and a merge circuit. The transaction layer processing channels are coupled to a data bus transmitting at least one packet data output by a data link layer circuit of the PCIe. The channel selection circuit receives packet start/end location information in a current clock cycle from the data link layer circuit, and distributes at least one packet data in the current clock cycle to at least one transaction layer processing channel according to the packet start/end location information. The merge circuit is coupled to the transaction layer processing channels and selectively merges transaction layer processing results output by the transaction layer processing channels based on the distribution of the packet data in the current clock cycle to the transaction layer processing channels via the channel selection circuit.

公开(公告)号：US20210365400A1

公开(公告)日：2021-11-25

申请号：US16931373

申请日：2020-07-16

Applicant: Faraday Technology Corp.

Inventor： Ching-Lin Hsu ,  Chang-Hsien Lin

IPC: G06F13/42 ,  G06F13/40

Abstract: An adaptor device including a first interface, a second interface, a negotiation circuit and a type C manager and controller is provided. The first interface is a universal serial bus (USB) 2.0 interface, and the second interface is a type C USB interface. When the first interface receives a first mode swap request, the type C manager and controller transmits a first mode swap signal in a type C format through the second interface according to the first mode swap request; when the second interface receives a second mode swap request, the negotiation circuit transmits a second mode swap signal in a USB 2.0 format through the first interface according to the second mode swap request.

公开(公告)号：US11177932B1

公开(公告)日：2021-11-16

申请号：US17234832

申请日：2021-04-20

Applicant: Faraday Technology Corp.

Inventor： Vinay Suresh Rao ,  Andrew Chao

IPC: H04L7/033 ,  H03M9/00 ,  H03H17/02

Abstract: A clock generation circuit for generating a plurality of output clocks includes: a differential circuit for receiving a single input clock signal and outputting two differential clock signals, and a DC signal; a first polyphase filter for generating four clock signals from the differential clock signals which are a quadrature phase apart from each other; a plurality of setting buffers for setting a same DC point for the four clock signals and generating four resultant clock signals; coupled polyphase filters for generating four more clock signals which are a quadrature apart from each other, and outputting the resultant eight clock signals; a phase mixer, for generating eight output clock signals 45 degrees apart from each other; and a plurality of restoration buffers for setting a DC point for each of the eight clock signals and generating eight output clock signals all riding on a same DC point.

公开(公告)号：US20210314202A1

公开(公告)日：2021-10-07

申请号：US17129799

申请日：2020-12-21

Applicant: Faraday Technology Corp.

Inventor： Shih-Yi Shih

IPC: H04L27/14 ,  H04L27/12 ,  H04L12/26 ,  H03M13/25

Abstract: The present invention discloses a Trellis-Coded-Modulation (TCM) decoder applied in a receiver, wherein the TCM decoder includes a branch metric unit, a path metric unit, a trace-back length selection circuit and a survival path management circuit. In operations of the TCM decoder, the branch metric unit is configured to receive multiple input codes to generate multiple sets of branch information. The path metric unit is configured to calculate multiple survival paths according to the multiple sets of branch information. The trace-back length selection circuit is configured to select a trace-back length, wherein the trace-back length is determined according to a signal quality of the receiver. The survival path management circuit is configured to return the multiple survival paths for the trace-back length in order to generate an output code.

公开(公告)号：US20210305990A1

公开(公告)日：2021-09-30

申请号：US17151673

申请日：2021-01-19

Applicant: FARADAY TECHNOLOGY CORPORATION ,  Faraday Technology Corp.

Inventor： Feng Xu ,  Chih-Yuan Hung ,  MENG ZHAO

IPC: H03M1/06

Abstract: A Successive Approximation Register Analog-to-Digital Converter (SAR ADC) is disclosed. The SAR ADC includes a switched capacitor array, a buffer, a comparator and a control logic circuit. The switched capacitor array is arranged to sample an input signal according to a switch control signal to generate a sampling signal. The buffer is arranged to generate a common mode voltage. The comparator is arranged to receive the sampling signal and the common mode voltage in order to generate a comparison result. The control logic circuit is arranged to generate an output signal according to the comparison result, and generate the switch control signal to control the switched capacitor array. The control logic circuit further generates an operation control signal to adjust a Miller compensation capacitor inside the buffer. An associated control method is also disclosed.