中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

43 records (took 0.045 seconds)

    Capacitor constructions with enhanced surface area
    31.
    发明授权
    Capacitor constructions with enhanced surface area 失效
    具有增强的表面积的电容器结构

    公开(公告)号：US07288808B2

    公开(公告)日：2007-10-30

    申请号：US10050334

    申请日：2002-01-15

    Applicant: Vishnu K. Agarwal ,  Garry A. Mercaldi

    Inventor： Vishnu K. Agarwal ,  Garry A. Mercaldi

    IPC: H01L27/108

    CPC classification number: H01L28/55 ,  H01L21/31604 ,  H01L21/31683 ,  H01L28/84 ,  H01L28/90 ,  Y10S438/964

    Abstract: A capacitor fabrication method may include forming a first capacitor electrode over a substrate, the first electrode having an inner surface area per unit area and an outer surface area per unit area that are both greater than an outer surface area per unit area of the substrate. A capacitor dielectric layer and a second capacitor electrode may be formed over the dielectric layer. The method may further include forming rugged polysilicon over the substrate, the first electrode being over the rugged polysilicon. Accordingly, the outer surface area of the first electrode can be at least 30% greater than the outer surface area of the substrate without the first electrode including polysilicon.

    Abstract translation: 电容器制造方法可以包括在衬底上形成第一电容器电极，第一电极具有每单位面积的内表面积和每单位面积的外表面积，其大于衬底的每单位面积的外表面积。 可以在电介质层上形成电容器电介质层和第二电容器电极。 该方法还可以包括在衬底上形成坚固的多晶硅，第一电极在坚固的多晶硅之上。 因此，第一电极的外表面积可以比不含第一电极包括多晶硅的衬底的外表面积大至少30％。

    Method for enhancing electrode surface area in DRAM cell capacitors
    32.
    发明授权
    Method for enhancing electrode surface area in DRAM cell capacitors 失效

    公开(公告)号：US07148555B2

    公开(公告)日：2006-12-12

    申请号：US10408358

    申请日：2003-04-07

    Applicant: Donald L Yates ,  Garry A Mercaldi ,  James J Hofmann

    Inventor： Donald L Yates ,  Garry A Mercaldi ,  James J Hofmann

    IPC: H01L29/00

    CPC classification number: H01L27/1085 ,  H01L27/10852 ,  H01L28/65 ,  H01L28/82 ,  H01L28/84 ,  H01L28/91

    Abstract: Methods for forming the lower electrode of a capacitor in a semiconductor circuit, and the capacitors formed by such methods are provided. The lower electrode is fabricated by forming a texturizing underlayer and then depositing a conductive material thereover. In one embodiment of a method of forming the lower electrode, the texturizing layer is formed by depositing a polymeric material comprising a hydrocarbon block and a silicon-containing block, over the insulative layer of a container, and then subsequently converting the polymeric film to relief or porous nanostructures by exposure to UV radiation and ozone, resulting in a textured porous or relief silicon oxycarbide film. A conductive material is then deposited over the texturizing layer resulting in a lower electrode have an upper roughened surface. In another embodiment of a method of forming the lower electrode, the texturizing underlayer is formed by depositing overlying first and second conductive metal layers and annealing the metal layers to form surface dislocations, preferably structured as a periodic network. A conductive metal is then deposited in gaseous phase, and agglomerates onto the surface dislocations of the texturizing layer, forming nanostructures in the form of island clusters. The capacitor is completed by depositing a dielectric layer over the formed lower electrode, and forming an upper capacitor electrode over the dielectric layer. The capacitors are particularly useful in fabricating DRAM cells.

    MRAM device fabricated using chemical mechanical polishing
    33.
    发明授权
    MRAM device fabricated using chemical mechanical polishing 有权
    使用化学机械抛光制造的MRAM器件

    公开(公告)号：US07119388B2

    公开(公告)日：2006-10-10

    申请号：US10721744

    申请日：2003-11-26

    Applicant: Donald L. Yates ,  Garry A. Mercaldi

    Inventor： Donald L. Yates ,  Garry A. Mercaldi

    IPC: H01L29/76 ,  H01L21/00

    CPC classification number: H01L27/222 ,  H01L43/12

    Abstract: The present invention provides a method of forming an MRAM cell which minimizes the occurrence of electrical shorts during fabrication. A first conductor is provided in a trench in an insulating layer and an upper surface of the insulating layer and the first conductor is planarized. Then, a first dielectric layer is deposited over the first conductor and insulating layer to a thickness at least greater than the thickness of a desired MRAM cell. The first dielectric layer is then patterned and etched to form an opening over the first conductor for the cell shapes. Then, the magnetic layers comprising the MRAM cell are consecutively formed within the cell shapes and the first dielectric layer.

    Abstract translation: 本发明提供一种形成MRAM单元的方法，该方法在制造期间使电短路的发生最小化。 第一导体设置在绝缘层中的沟槽中，绝缘层的上表面和第一导体被平坦化。 然后，将第一介电层沉积在第一导体和绝缘层上方至少大于所需MRAM单元厚度的厚度。 然后对第一介电层进行图案化和蚀刻，以在单元形状的第一导体上形成开口。 然后，包含MRAM单元的磁性层在单元格形状和第一介电层内连续地形成。

    Method and composite for decreasing charge leakage
    36.
    发明授权
    Method and composite for decreasing charge leakage 有权
    减少电荷泄漏的方法和复合材料

    公开(公告)号：US06791148B2

    公开(公告)日：2004-09-14

    申请号：US10369786

    申请日：2003-02-18

    Applicant: Michael Nuttall ,  Garry A. Mercaldi

    Inventor： Michael Nuttall ,  Garry A. Mercaldi

    IPC: H01L2976

    CPC classification number: H01L21/28273 ,  H01L29/42324 ,  H01L29/511 ,  Y10S438/954

    Abstract: A dielectric insulating composite for insulating a floating gate from a control gate in a non-volatile memory is described. A material, such as an undoped polysilicon, amorphous silicon, or amorphous polysilicon or a silicon rich nitride, is inserted in the gate structure. The oxide film that results from the oxidation of these films is relatively free from impurities. As a result, charge leakage between the floating gate and control gate is reduced.

    Abstract translation: 描述了用于将浮动栅极与非易失性存储器中的控制栅极绝缘的绝缘绝缘复合材料。 诸如未掺杂的多晶硅，非晶硅或无定形多晶硅或富含硅的氮化物的材料插入栅极结构中。 由这些膜的氧化产生的氧化膜相对不含杂质。 结果，浮栅和控制栅之间的电荷泄漏减小。

    Modifying material removal selectivity in semiconductor structure development
    38.
    发明授权
    Modifying material removal selectivity in semiconductor structure development 失效
    改善半导体结构开发中的材料去除选择性

    公开(公告)号：US06639266B1

    公开(公告)日：2003-10-28

    申请号：US09651470

    申请日：2000-08-30

    Applicant: Donald L. Yates ,  Garry A. Mercaldi

    Inventor： Donald L. Yates ,  Garry A. Mercaldi

    IPC: H01L27108

    CPC classification number: H01L28/91 ,  H01L21/31056 ,  H01L27/10855 ,  H01L28/84

    Abstract: Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize localized masking of holes for protection of the inside of the holes during non-mechanical removal of exposed surface layers. The localized masking is accomplished through differential exposure of a resist layer to electromagnetic or thermal energy. The methods further include modifying the removal selectivity of the surface material relative to material protected by the localized masking. Modification of the removal selectivity eases or quickens removal of the surface material. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

    Abstract translation: 用于集成电路的容器结构及其制造方法，而不使用机械平面化（例如化学机械平面化（CMP）），从而消除了CMP引起的缺陷和变化。 该方法利用在非机械去除暴露的表面层期间的孔的局部掩蔽来保护孔的内部。 通过将抗蚀剂层与电磁或热能的差分曝光来实现局部掩蔽。 所述方法还包括改变表面材料相对于通过局部掩蔽保护的材料的去除选择性。 去除选择性的改性缓和或加快了表面材料的去除。 容器结构适用于并入这种存储单元的存储器单元和装置以及其它集成电路。

Patent Agency Ranking