公开(公告)号：US07020832B2

公开(公告)日：2006-03-28

申请号：US10039005

申请日：2001-12-31

Applicant: In San Jeon ,  Hyuk Kim ,  Woo Seok Yang ,  Kyung Soo Kim ,  Whan Woo Kim ,  Han Jin Cho

Inventor： In San Jeon ,  Hyuk Kim ,  Woo Seok Yang ,  Kyung Soo Kim ,  Whan Woo Kim ,  Han Jin Cho

IPC: H03M13/03

CPC classification number: H03M13/3922 ,  H03M13/2957 ,  H03M13/6502 ,  H03M13/6505

Abstract: The present invention relates to a turbo decoder having a state metric, a calculating method using the turbo decoder and a computer-readable recoding medium for executing a calculation method implemented to the turbo decoder. The turbo decoder includes branch metric calculation unit, state metric calculation unit and log likelihood ratio calculation unit. The present invention may reduce calculation steps by simplifying a conventional turbo decode algorithm, reducing a size of a hardware, which the turbo decoder can be implemented in as an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA). The present invention can be implemented in an error correction in wireless communication system and satellite communication system.

公开(公告)号：US06917218B2

公开(公告)日：2005-07-12

申请号：US10683228

申请日：2003-10-10

Applicant: Won Jong Kim ,  Seung Chul Kim ,  Han Jin Cho ,  Kwang Youb Lee

Inventor： Won Jong Kim ,  Seung Chul Kim ,  Han Jin Cho ,  Kwang Youb Lee

IPC: G06F7/52 ,  G06F7/72 ,  H03K19/173

CPC classification number: G06F7/724

Abstract: The present invention relates to a finite field multiplier used for implementing an encrypting algorithm circuit, thereby minimizing power consumption and circuit area in implementing the finite field multiplier with a LFSR (Linear Feedback Shift Register) structure. The Finite field multiplier of the present invention is an operator performing a modular operation on the multiplication result of two data represented on a polynomial basis in a Galois Field into an irreducible polynomial. The LFSR structure is a serial finite field multiplication structure, and has a merit over an array structure and a hybrid structure in application to systems that are limited in size and power due to its simplicity of circuits and also its capability of being implemented in a small size.

Abstract translation: 本发明涉及一种用于实现加密算法电路的有限域乘法器，从而使用LFSR（线性反馈移位寄存器）结构实现有限域乘法器的功耗和电路面积最小化。 本发明的有限域乘法器是对在Galois域中的多项式基上表示的两个数据的相乘结果进行不可约多项式的模拟运算的运算符。 LFSR结构是串行有限域乘法结构，并且具有阵列结构和混合结构的优点，适用于由于其简单的电路而受到限制和功率限制的系统，并且还具有以小的方式实现的能力 尺寸。

公开(公告)号：US6154300A

公开(公告)日：2000-11-28

申请号：US968944

申请日：1997-11-12

Applicant: Han-Jin Cho

Inventor： Han-Jin Cho

IPC: H01Q15/00 ,  H04B10/114 ,  H04B10/00

CPC classification number: H04B10/1149

Abstract: A wireless data communication apparatus using the diffused infrared-ray antennas comprising: a plurality of terminals having their own optical communication modules for transmitting and receiving infrared-ray signals, wherein the optical communication module includes a parabolic shaped infrared-ray antenna; and a repeater which receives the infrared-ray signals transmitted from the plurality of terminals and transmits the infrared-ray signals to the plurality of terminals, wherein the repeater includes a parabolic shaped infrared-ray antenna.

Abstract translation: 一种使用扩散红外线天线的无线数据通信装置，包括：具有各自的用于发送和接收红外线信号的光通信模块的多个终端，其中所述光通信模块包括抛物线形红外线天线; 以及中继器，其接收从所述多个终端发送的红外线信号，并将所述红外线信号发送到所述多个终端，其中所述中继器包括抛物线形红外线天线。

公开(公告)号：US08890570B2

公开(公告)日：2014-11-18

申请号：US13607637

申请日：2012-09-07

Applicant: Han Jin Cho ,  Young Hwan Bae

Inventor： Han Jin Cho ,  Young Hwan Bae

IPC: H01L25/00 ,  H03K19/173 ,  G11C5/06

CPC classification number: H03K19/17744 ,  H03K19/1737 ,  H03K19/1776

Abstract: A switch block circuit in a field programmable gate array is provided. The switch block circuit includes a configuration memory unit including first group memories and second group memories and a switching unit including first group switching transistors and second group switching transistors. The switch block circuit further includes a selection unit for correspondingly connecting the second group memories with the second group switching transistors depending on an operation mode. The switch block is efficiently reconfigurable depending on the intended use, and configuration memories unused in a specific operation mode may be applied to other purposes.

Abstract translation: 提供现场可编程门阵列中的开关块电路。 开关块电路包括配置存储单元，其包括第一组存储器和第二组存储器，以及包括第一组开关晶体管和第二组开关晶体管的开关单元。 开关块电路还包括用于根据操作模式相应地将第二组存储器与第二组开关晶体管连接的选择单元。 切换块根据预期用途有效地可重新配置，并且在特定操作模式中未使用的配置存储器可以应用于其他目的。

公开(公告)号：US08564360B2

公开(公告)日：2013-10-22

申请号：US13440497

申请日：2012-04-05

Applicant: Yong Il Kwon ,  Han Jin Cho ,  Tah Joon Park ,  Koon Shik Cho

Inventor： Yong Il Kwon ,  Han Jin Cho ,  Tah Joon Park ,  Koon Shik Cho

IPC: G05F1/10

CPC classification number: G06F1/32

Abstract: Disclosed herein is a pad controlling apparatus controlling current and voltage applied to a pad, the pad controlling apparatus including: a voltage drop unit dropping the voltage applied to the pad; a switching unit connected in parallel with the voltage drop unit; and a control unit comparing a level of the dropped voltage and first reference voltage with each other and turning on the switching unit on when the level of the dropped voltage is larger than the first reference voltage. According to the present invention, even though interrupt occurs from the outside, a chip may be normally operated.

Abstract translation: 这里公开了一种控制施加到焊盘的电流和电压的焊盘控制装置，焊盘控制装置包括：降压单元，降低施加到焊盘的电压; 开关单元，与所述电压降单元并联连接; 以及控制单元，其将所述下降电压和所述第一参考电压的电平相互比较，并且在所述下降电压的电平大于所述第一参考电压时接通所述开关单元。 根据本发明，即使从外部发生中断，芯片也可以正常工作。

公开(公告)号：US20120268197A1

公开(公告)日：2012-10-25

申请号：US13440497

申请日：2012-04-05

Applicant: Yong Il Kwon ,  Han Jin Cho ,  Tah Joon Park ,  Koon Shik Cho

Inventor： Yong Il Kwon ,  Han Jin Cho ,  Tah Joon Park ,  Koon Shik Cho

IPC: G05F3/02

CPC classification number: G06F1/32

Abstract: Disclosed herein is a pad controlling apparatus controlling current and voltage applied to a pad, the pad controlling apparatus including: a voltage drop unit dropping the voltage applied to the pad; a switching unit connected in parallel with the voltage drop unit; and a control unit comparing a level of the dropped voltage and first reference voltage with each other and turning on the switching unit on when the level of the dropped voltage is larger than the first reference voltage. According to the present invention, even though interrupt occurs from the outside, a chip may be normally operated.

Abstract translation: 这里公开了一种控制施加到焊盘的电流和电压的焊盘控制装置，焊盘控制装置包括：降压单元，降低施加到焊盘的电压; 开关单元，与所述电压降单元并联连接; 以及控制单元，其将所述下降电压和所述第一参考电压的电平相互比较，并且在所述下降电压的电平大于所述第一参考电压时接通所述开关单元。 根据本发明，即使从外部发生中断，芯片也可以正常工作。

公开(公告)号：US08275032B2

公开(公告)日：2012-09-25

申请号：US12142708

申请日：2008-06-19

Applicant: June Young Chang ,  Han Jin Cho ,  Guee Sang Lee ,  Young Hwan Bae ,  In San Jeon ,  Won Jong Kim ,  Mi Young Lee ,  Ju Yeob Kim

Inventor： June Young Chang ,  Han Jin Cho ,  Guee Sang Lee ,  Young Hwan Bae ,  In San Jeon ,  Won Jong Kim ,  Mi Young Lee ,  Ju Yeob Kim

IPC: H04B1/66

CPC classification number: H04N19/137 ,  H04N19/115 ,  H04N19/61

Abstract: There are provided a distributed video coding apparatus and method capable of controlling an encoding rate, the apparatus including: an intra-frame encoder encoding a key frame and outputting a bit stream of the encoded key frame; an encoder rate control (ERC) module calculating a bit rate according to motion complexity of a present Wyner-Ziv (WZ) frame by using a correlation between the motion complexity and the bit rate; and a turbo encoder encoding the present WZ frame by the bit rate calculated at the ERC module and outputting the encoded WZ bit stream.

Abstract translation: 提供了一种能够控制编码率的分布式视频编码装置和方法，该装置包括：编码关键帧并输出编码关键帧的比特流的帧内编码器; 编码器速率控制（ERC）模块，通过使用运动复杂度和比特率之间的相关性，根据当前Wyner-Ziv（WZ）帧的运动复杂度来计算比特率; 以及通过在ERC模块处计算出的比特率编码当前WZ帧并输出编码的WZ比特流的turbo编码器。

公开(公告)号：US20100142620A1

公开(公告)日：2010-06-10

申请号：US12630827

申请日：2009-12-03

Applicant: Mi Young LEE ,  Han Jin CHO

Inventor： Mi Young LEE ,  Han Jin CHO

IPC: H04N7/26

CPC classification number: H04N19/395 ,  H04N19/51

Abstract: Disclosed is a technique that shifts the position of a motion compensation block by an error of a motion field and then performs motion compensation to estimate a current frame from past and future frames in digital video coding (DVC), thereby enhancing the accuracy of current frame estimation results.

Abstract translation: 公开了一种通过运动场的误差移动运动补偿块的位置，然后进行运动补偿以估计数字视频编码（DVC）中的过去和未来帧的当前帧，从而提高当前帧的精度 估计结果。

公开(公告)号：US07711787B2

公开(公告)日：2010-05-04

申请号：US11300731

申请日：2005-12-14

Applicant: Jin Ho Han ,  Young Hwan Bae ,  Han Jin Cho ,  Jun Young Chang

Inventor： Jin Ho Han ,  Young Hwan Bae ,  Han Jin Cho ,  Jun Young Chang

IPC: G06F15/16

CPC classification number: H04L49/10 ,  H04L49/109 ,  H04L49/3009 ,  H04L49/3018 ,  H04L49/503

Abstract: An on-chip network interfacing apparatus and method are provided. The apparatus includes a plurality of on-chip network ports; a switch receiving data from a first on-chip network port of the on-chip network ports and transmitting the received data to a second on-chip network port of the on-chip network ports; and an interface unit interfacing an advanced microcontroller bus architecture (AMBA) signal received from an module, which is designed according to an AMBA on-chip bus protocol, and outputting the interfacing result to the first on-chip network port; and interfacing the on-chip network signal received from the first on-chip network port, and outputting the interfacing result to the module. Accordingly, it is possible to establish communications at increased speeds by interfacing a signal according to the AMBA 2.0 on-chip bus protocol with a signal according to the on-chip network protocol.

Abstract translation: 提供了片上网络接口设备和方法。 该装置包括多个片上网络端口; 从所述片上网络端口的第一片上网络端口接收数据并将所接收的数据发送到所述片上网络端口的第二片上网络端口; 以及接口单元，其连接从根据AMBA片上总线协议设计的模块接收的高级单片机总线架构（AMBA）信号，并将所述接口结果输出到所述第一片上网络端口; 并且连接从第一片上网络端口接收的片上网络信号，并将接口结果输出到模块。 因此，可以通过将根据AMBA 2.0片上总线协议的信号与根据片上网络协议的信号进行接口来以增加的速度建立通信。

公开(公告)号：US20090158285A1

公开(公告)日：2009-06-18

申请号：US12239508

申请日：2008-09-26

Applicant: Mi Young Lee ,  Han Jin Cho

Inventor： Mi Young Lee ,  Han Jin Cho

IPC: G06F9/46

CPC classification number: G06F9/5011 ,  G06F2209/5014

Abstract: An apparatus for controlling a resource sharing schedule in a multi-decoding system including a multi-decoder formed of a plurality of resources, the apparatus including: a storage unit storing status information of the resources and information required in controlling the resource sharing schedule; and a controller, when a source resource requests assignment of a target resource, assigning the target resource, outputting information of the target resource to the source resource, and updating statuses of the resources, wherein the apparatus controls the resource sharing schedule while bidirectionally connected to the resources to share the resources between the multi-decoders. Accordingly, it is possible to reduce an overall decoding time and controlling a resource usage schedule.

Abstract translation: 一种用于在包括由多个资源构成的多解码器的多解码系统中控制资源共享调度的装置，所述装置包括：存储单元，存储资源的状态信息和控制资源共享进度所需的信息; 以及控制器，当源资源请求分配目标资源时，分配所述目标资源，将所述目标资源的信息输出到所述源资源，以及更新所述资源的状态，其中，所述装置控制所述资源共享进度，同时双向地连接到 资源共享多解码器之间的资源。 因此，可以减少整体解码时间并控制资源使用进度。