公开(公告)号：US07074689B2

公开(公告)日：2006-07-11

申请号：US10935520

申请日：2004-09-07

Applicant: Martin Gutsche ,  Harald Seidl

Inventor： Martin Gutsche ,  Harald Seidl

IPC: H01L21/20

CPC classification number: H01L27/10867 ,  H01L27/10829 ,  H01L27/1087 ,  H01L29/66181

Abstract: The present invention provides a method for fabricating a trench capacitor having an insulation collar (10; 10a, 10b) in a substrate (1), which is electrically connected to the substrate (1) on one side via a buried contact (15a, 15b), in particular for a semiconductor memory cell having a planar select transistor which is provided in the substrate (1) and is connected via the buried contact (15a, 15b), comprising the steps of: providing a trench (5) in the substrate (1) using a hard mask (2, 3) with a corresponding mask opening; providing a capacitor dielectric (30) in the lower and middle regions of the trench, the insulation collar (10) in the middle and upper regions of the trench and an electrically conductive filling (20) at least up to the top side of the insulation collar (10); completely filling the trench (5) with a filling material (50; 50′; 50″; 20); carrying out an STI trench production process; removing the filling material (50; 50′; 50″; 20) and lowering the electrically conductive filling (20) to below the top side of the insulation collar (10); forming an insulation region (IS; IS1, IS2) on one side with respect to the substrate (1) above the insulation collar (10); uncovering a connection region (KS; KS1, KS2) on the other side with respect to the substrate (1) above the insulation collar (10); and forming the buried contact (15a, 15b) by depositing and etching back a C filling (70; 70′; 70″; 70′″).

Abstract translation: 本发明提供一种用于制造在衬底（1）中具有绝缘套环（10; 10a，10b）的沟槽电容器的方法，所述衬底（1）通过埋入触点（15）电连接到衬底（1） a）15b），特别是具有设置在基板（1）中并通过埋入触点（15a，15b）连接的平面选择晶体管的半导体存储单元，包括以下步骤：提供沟槽 （5）在使用具有对应的掩模开口的硬掩模（2,3）的基板（1）中; 在所述沟槽的下部和中部区域中提供电容器电介质（30），所述沟槽的中部和上部区域中的所述绝缘环（10）和至少直到所述绝缘体的顶侧的导电填料（20） 衣领（10）; 用填充材料（50; 50'; 50“; 20）完全填充沟槽（5）; 开展STI沟槽生产工艺; 去除所述填充材料（50; 50'; 50“; 20）并将所述导电填料（20）降低到所述绝缘套环（10）的顶侧下方; 在所述绝缘套环（10）上方相对于所述衬底（1）在一侧上形成绝缘区域（IS; IS 1，IS 2）; 相对于绝缘套环（10）上方的基板（1）露出另一侧的连接区域（KS; KS 1，KS 2）; 以及通过沉积和蚀刻C填充物（70; 70'; 70“，70”'）来形成所述埋入触点（15a，15b）。

公开(公告)号：US20060125108A1

公开(公告)日：2006-06-15

申请号：US11296740

申请日：2005-12-07

Applicant: Martin Gutsche ,  Harald Seidl

Inventor： Martin Gutsche ,  Harald Seidl

IPC: H01L23/48

CPC classification number: H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1683

Abstract: In a method for producing a microelectronic electrode structure a first wiring plane is prepared, an insulating region on the first wiring plane is provided, a through-hole in the insulating region is formed, a ring electrode in the through-hole is formed, and a second wiring plane is formed on the insulating region. The ring electrode comprises a first side and a second side, the ring electrode is electrically connected on the first side to the first wiring plane, and the second wiring plane is electrically connected to the second side of the ring electrode.

Abstract translation: 在制造微电子电极结构体的方法中，制备第一布线面，设置第一布线面上的绝缘区域，形成绝缘区域的贯通孔，形成通孔内的环状电极， 在绝缘区域上形成第二布线平面。 环形电极包括第一侧和第二侧，环形电极在第一侧电连接到第一布线平面，并且第二布线平面电连接到环形电极的第二侧。

公开(公告)号：US20060079064A1

公开(公告)日：2006-04-13

申请号：US11229868

申请日：2005-09-19

Applicant: Harald Seidl

Inventor： Harald Seidl

IPC: H01L21/20

CPC classification number: H01L29/66181 ,  H01L27/10829 ,  H01L27/10861

Abstract: Fabrication method for a trench capacitor having an insulation collar which on one side is electrically connected to a substrate via a buried contact, in particular for a semiconductor memory cell, and corresponding trench capacitor The present invention provides a fabrication method for a trench capacitor having an insulation collar (10; 10a, 10b) in a substrate (1), which on one side is electrically connected to the substrate (1) via a buried contact (15a, 15b), comprising the steps of: providing a trench (5) in the substrate (1) using a hard mask (2, 3) with a corresponding mask opening; providing a capacitor dielectric (30) in the lower and middle trench regions, the insulation collar (10) in the middle and upper trench regions and an electrically conductive filling (20) at least as far as the top side of the insulation collar (10), with the top side of the insulation collar (10) being at a distance from the top side (OS) of the substrate (1); causing the electrically conductive filling (20) to recede to below the top side of the insulation collar (10); on one side, forming an insulation region (IS; IS1, IS2) with respect to the substrate (1) above the insulation collar (10); on the other side, forming a terminal region (KS; KS1, KS2) with respect to the substrate (1) above the insulation collar (10); providing an interface layer (100) of a transition metal nitride on the terminal region (KS; KS1, KS2); and forming the buried contact (15a, 15b) by depositing and etching back a conductive filling (70). The invention also provides a corresponding trench capacitor.

公开(公告)号：US20060019447A1

公开(公告)日：2006-01-26

申请号：US11185584

申请日：2005-07-20

Applicant: Martin Gutsche ,  Harald Seidl

Inventor： Martin Gutsche ,  Harald Seidl

IPC: H01L21/336 ,  H01L21/338

CPC classification number: H01L29/66621 ,  H01L21/823412 ,  H01L21/823437 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/7834

Abstract: The present invention provides a process for producing a gate element for a transistor, in which a substrate (101) is provided, an insulation layer (104) and a sacrificial layer (105) are deposited on the substrate (101), the sacrificial layer (105) is patterned and a spacing layer (107) is deposited on the sacrificial layer, the spaces in the patterned sacrificial layer (105) are filled with a filling layer (108), the sacrificial layer structure (105a, 105b) and regions of the insulation layer (104) which are located beneath the sacrificial layer structure (105a, 105b) are removed. Finally, recesses (110) are etched into the substrate (101), the spacing layer (107) and those regions of the insulation layer which are not covered by the filling layer (108) are removed, a gate oxide layer (111) of the gate element is deposited and a gate electrode layer (112) of the gate element is deposited in the recesses (110). After the filling layer (108) has been removed, the result is a gate element for a field effect transistor with a low leakage current which can advantageously be used as a select transistor for a memory cell of a memory cell array.

Abstract translation: 本发明提供了一种用于制造晶体管的栅极元件的方法，其中提供衬底（101），在衬底（101）上沉积绝缘层（104）和牺牲层（105），牺牲层 （105）被图案化并且在牺牲层上沉积间隔层（107），图案化牺牲层（105）中的空间填充有填充层（108），牺牲层结构（105a，105b） 并且去除位于牺牲层结构（105a，105b）下方的绝缘层（104）的区域。 最后，将凹槽（110）蚀刻到衬底（101）中，去除间隔层（107）和未被填充层（108）覆盖的绝缘层的那些区域，去除栅极氧化物层（111） 沉积栅极元件，并且栅极元件的栅电极层（112）沉积在凹槽（110）中。 在填充层（108）已经被去除之后，结果是用于具有低泄漏电流的场效应晶体管的栅极元件，其可以有利地用作存储器单元阵列的存储器单元的选择晶体管。

公开(公告)号：US20060001067A1

公开(公告)日：2006-01-05

申请号：US11127505

申请日：2005-05-12

Applicant: Martin Gutsche ,  Harald Seidl

Inventor： Martin Gutsche ,  Harald Seidl

IPC: H01L29/00 ,  H01L21/20

CPC classification number: H01L28/92 ,  H01L27/0805 ,  H01L27/1087 ,  H01L28/91 ,  H01L29/66181 ,  H01L29/945

Abstract: The present invention provides a fabrication method for a semiconductor structure having integrated capacitors and a corresponding semiconductor structure. The fabrication method has the following steps of: providing a semiconductor substrate (1; 1′, 60, 1″) having a front side (VS) and a rear side (RS); providing trenches (5) in the semiconductor substrate (1; 1′, 60, 1″) proceeding from the front side (VS) of the semiconductor substrate (1; 1′, 60, 1″); providing a respective inner capacitor electrode (6) in the trenches (5); uncovering the inner capacitor electrodes (6) proceeding from the rear side (RS) of the semiconductor substrate (1; 1′, 60, 1″); providing a capacitor dielectric (40) on the uncovered inner capacitor electrodes (6); and providing outer capacitor electrodes (50) on the capacitor dielectric (40) on the inner capacitor electrodes (6).

Abstract translation: 本发明提供一种具有集成电容器和相应的半导体结构的半导体结构的制造方法。 该制造方法具有以下步骤：提供具有前侧（VS）和后侧（RS）的半导体衬底（1; 1'，60“1”）; 在半导体衬底（1; 1'，60“1”）的前侧（VS）上提供在半导体衬底（1; 1'，60“1”）中的沟槽（5） 在沟槽（5）中提供相应的内部电容器电极（6）; 露出从半导体衬底（1; 1'，60,1“）的后侧（RS）延伸的内部电容器电极（6）; 在未覆盖的内部电容器电极（6）上提供电容器电介质（40）; 以及在内部电容器电极（6）上的电容器电介质（40）上提供外部电容器电极（50）。

公开(公告)号：US06953722B2

公开(公告)日：2005-10-11

申请号：US10425461

申请日：2003-04-29

Applicant: Harald Seidl ,  Martin Gutsche ,  Thomas Hecht ,  Stefan Jakschik ,  Stephan Kudelka ,  Uwe Schröder ,  Matthias Schmeide

Inventor： Harald Seidl ,  Martin Gutsche ,  Thomas Hecht ,  Stefan Jakschik ,  Stephan Kudelka ,  Uwe Schröder ,  Matthias Schmeide

IPC: H01L21/311 ,  H01L21/8242

CPC classification number: H01L27/10867 ,  H01L21/31133

Abstract: In a method for forming patterned ceramic layers, a ceramic material is deposited on a substrate and is subsequently densified by heat treatment, for example. In this case, the initially amorphous material is converted into a crystalline or polycrystalline form. In order that the now crystalline material can be removed again from the substrate, imperfections are produced in the ceramic material, for example by ion implantation. As a result, the etching medium can more easily attack the ceramic material, so that the latter can be removed with a higher etching rate. Through inclined implantation, the method can be performed in a self-aligning manner and the ceramic material can be removed on one side, by way of example, in trenches or deep trench capacitors.

Abstract translation: 在用于形成图案化陶瓷层的方法中，陶瓷材料沉积在基底上，并随后通过热处理致密化。 在这种情况下，最初的无定形材料被转化为结晶或多晶形式。 为了现在的结晶材料可以再次从衬底去除，例如通过离子注入在陶瓷材料中产生缺陷。 结果，蚀刻介质可以更容易地侵蚀陶瓷材料，使得后者可以以更高的蚀刻速率被去除。 通过倾斜注入，该方法可以以自对准的方式进行，并且陶瓷材料可以通过例如在沟槽或深沟槽电容器中被一侧除去。

公开(公告)号：US20050191806A1

公开(公告)日：2005-09-01

申请号：US11055431

申请日：2005-02-10

Applicant: Martin Gutsche ,  Harald Seidl

Inventor： Martin Gutsche ,  Harald Seidl

IPC: H01L21/8242 ,  H01L27/108 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L27/1087

Abstract: The invention provides a method for fabricating a memory cell for storing electric charge, which has a substrate (101), which forms a first electrode, a trench-like recess (102) etched into the substrate (101), conductive material, which is provided as a projection in a central region of the trench-like recess (102) and spaced apart from the side walls (107) of the trench-like recess (102) and is in electrical contact with the substrate at the base (104) of the trench-like recess (102), a dielectric layer (108), which has been deposited on the side walls (107) of the trench-like recess (102), the base (104) of the trench-like recess (102) and the surfaces of the conductive material (105), and an electrode layer (110), which has been deposited on the dielectric layer (108) and forms a second electrode.

Abstract translation: 本发明提供了一种用于制造用于存储电荷的存储单元的方法，该方法具有形成第一电极的基板（101），蚀刻到基板（101）中的沟槽状凹部（102），导电材料 设置为在所述沟槽状凹部（102）的中心区域中并与所述沟槽状凹部（102）的侧壁（107）间隔开并且与所述基底（104）处的所述基板电接触的突起， 已经沉积在沟槽状凹部（102）的侧壁（107）上的电介质层（108），沟槽状凹部（102）的基底（104） 102）和导电材料（105）的表面以及已经沉积在电介质层（108）上并形成第二电极的电极层（110）。

公开(公告)号：US08704338B2

公开(公告)日：2014-04-22

申请号：US13247162

申请日：2011-09-28

Applicant: Gunther Mackh ,  Gerhard Leschik ,  Adolf Koller ,  Harald Seidl

Inventor： Gunther Mackh ,  Gerhard Leschik ,  Adolf Koller ,  Harald Seidl

IPC: H01L23/544 ,  H01L21/78

CPC classification number: H01L21/78 ,  G06F17/5068 ,  H01L21/82 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A chip includes a dielectric layer and a fill structure in the dielectric layer, wherein the fill structure extends along a dicing edge of the chip, with the fill structure abutting the dicing edge.

Abstract translation: 芯片包括电介质层中的电介质层和填充结构，其中填充结构沿芯片的切割边缘延伸，填充结构邻接切割边缘。

公开(公告)号：US08525347B2

公开(公告)日：2013-09-03

申请号：US11416712

申请日：2006-05-03

Applicant: Hans-Joachim Barth ,  Harald Seidl

Inventor： Hans-Joachim Barth ,  Harald Seidl

IPC: H01L23/52

CPC classification number: H01L24/95 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/31053 ,  H01L21/31058 ,  H01L21/3185 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2924/14 ,  Y10T156/12 ,  H01L2924/00

Abstract: The present disclosures relates to a method for producing ultrathin chip stacks and chip stacks. Generally, a plurality of first semiconductor chips is formed in a wafer. A second semiconductor chip is applied to each of the plurality of first semiconductor chips via a connection layer and a stabilization layer is applied to fill in the interspace between each of the second semiconductor chips. The wafer, semiconductor chip, and stabilization layer are thinned and the wafer is sawed to produce a plurality of singulated chip stacks.

公开(公告)号：US08420526B2

公开(公告)日：2013-04-16

申请号：US13167744

申请日：2011-06-24

Applicant: Martin Gutsche ,  Franz Kreupl ,  Harald Seidl

Inventor： Martin Gutsche ,  Franz Kreupl ,  Harald Seidl

IPC: H01L21/4763

CPC classification number: H01L27/24 ,  B82Y10/00 ,  H01L21/28525 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76889 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/228 ,  H01L2221/1094

Abstract: The present invention relates to a method for producing a vertical interconnect structure, a memory device and an associated production method, in which case, after the formation of a contact region in a carrier substrate a catalyst is produced on the contact region and a free-standing electrically conductive nanoelement is subsequently formed between the catalyst and the contact region and embedded in a dielectric layer.