公开(公告)号：US20100006983A1

公开(公告)日：2010-01-14

申请号：US12548723

申请日：2009-08-27

Applicant: Martin Gutsche ,  Harald Seidl

Inventor： Martin Gutsche ,  Harald Seidl

IPC: H01L29/00

CPC classification number: H01L21/0337 ,  H01L21/0338 ,  H01L21/30604

Abstract: A layer structure and process for providing sublithographic structures are provided. A first auxiliary layer is formed over a surface of a carrier layer. A lithographically patterned second auxiliary layer structure is formed on a surface of the first auxiliary layer. The first auxiliary layer is anisotropically etched using the patterned second auxiliary layer structure as mask to form an anisotropically patterned first auxiliary layer structure. The anisotropically patterned first auxiliary layer structure is isotropically etched back using the patterned second auxiliary layer structure to remove subsections below the second auxiliary layer structure and to form an isotropically patterned first auxiliary layer structure. A mask layer is formed over the carrier layer including the subsections beneath the second auxiliary layer structure and is anisotropically etched down to the carrier layer to form the sublithographic structures. The first and second auxiliary layer structures are removed to uncover the sublithographic structures

Abstract translation: 提供了用于提供亚光刻结构的层结构和工艺。 在载体层的表面上形成第一辅助层。 在第一辅助层的表面上形成光刻图案化的第二辅助层结构。 使用图案化的第二辅助层结构作为掩模对第一辅助层进行各向异性蚀刻，以形成各向异性图案化的第一辅助层结构。 各向异性图案化的第一辅助层结构使用图案化的第二辅助层结构进行各向同性地回蚀，以除去第二辅助层结构之下的部分并形成各向同性图案化的第一辅助层结构。 掩模层形成在载体层上，包括第二辅助层结构下面的子部分，并且各向异性地向下蚀刻到载体层以形成亚光刻结构。 去除第一和第二辅助层结构以露出​​亚光刻结构

公开(公告)号：US07323357B2

公开(公告)日：2008-01-29

申请号：US11280864

申请日：2005-11-17

Applicant: Harald Seidl

Inventor： Harald Seidl

IPC: H01L21/06

CPC classification number: H01L45/06 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1691

Abstract: The invention relates to a method for manufacturing at least one phase change memory cell. The method at least fabricating at least one first lamellar spacer of conductive material, which is electrically coupled to the PCM material of the memory cell; fabricating at least one second lamellar spacer on top of the first lamellar spacer, wherein the second lamellar spacer crosses the first lamellar spacer in the area of the PCM material; partially removing the first lamellar spacer, wherein the second lamellar spacer serves as a hardmask for partially removing the first lamellar spacer, so that the first lamellar spacer forms at least one electrode contacting an area of PCM material.

Abstract translation: 本发明涉及一种用于制造至少一个相变存储器单元的方法。 该方法至少制造导电材料的至少一个第一层状间隔物，其电耦合到存储单元的PCM材料; 在所述第一层状间隔物的顶部上制造至少一个第二层状间隔物，其中所述第二层状间隔物穿过所述PCM材料区域中的所述第一层状间隔物; 部分地去除第一层状间隔物，其中第二层状间隔物用作用于部分去除第一层状间隔物的硬掩模，使得第一层状间隔物形成接触PCM材料区域的至少一个电极。

公开(公告)号：US20070105333A1

公开(公告)日：2007-05-10

申请号：US11588769

申请日：2006-10-27

Applicant: Martin Gutsche ,  Franz Kreupl ,  Harald Seidl

Inventor： Martin Gutsche ,  Franz Kreupl ,  Harald Seidl

IPC: H01L29/76 ,  H01L21/20

CPC classification number: H01L27/24 ,  B82Y10/00 ,  H01L21/28525 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76889 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/228 ,  H01L2221/1094

Abstract: The present invention relates to a method for producing a vertical interconnect structure, a memory device and an associated production method, in which case, after the formation of a contact region in a carrier substrate a catalyst is produced on the contact region and a free-standing electrically conductive nanoelement is subsequently formed between the catalyst and the contact region and embedded in a dielectric layer.

Abstract translation: 本发明涉及垂直互连结构的制造方法，存储装置及相关的制造方法，在这种情况下，在载体基板上形成接触区域之后，在接触区域上产生催化剂， 随后在催化剂和接触区域之间形成立体导电的纳米元素并嵌入电介质层。

公开(公告)号：US20060264054A1

公开(公告)日：2006-11-23

申请号：US11100325

申请日：2005-04-06

Applicant: Martin Gutsche ,  Thomas Hecht ,  Harald Seidl ,  Uwe Rudolph ,  Barbara Lorenz ,  Elisabeth Weikmann

Inventor： Martin Gutsche ,  Thomas Hecht ,  Harald Seidl ,  Uwe Rudolph ,  Barbara Lorenz ,  Elisabeth Weikmann

IPC: H01L21/465

CPC classification number: H01L21/30655 ,  H01L21/743 ,  H01L21/76898

Abstract: The present invention relates to a method for etching a trench in a semiconductor substrate. More specifically, the present invention relates to a method for etching deep trenches such as those having aspect ratios of 30 and higher. According to embodiments of the invention, a method for etching a trench in a semiconductor substrate includes a first etch cycle wherein the trench is etched to a first depth. Thereafter, a protective liner is deposited on at least the upper part of the trench's sidewalls. The protective liner includes inorganic material. During at least one second etch cycle, the trench is etched to its final depth.

Abstract translation: 本发明涉及一种用于蚀刻半导体衬底中的沟槽的方法。 更具体地说，本发明涉及一种蚀刻深沟槽的方法，例如具有30或更高的纵横比的那些。 根据本发明的实施例，用于蚀刻半导体衬底中的沟槽的方法包括第一蚀刻循环，其中沟槽被蚀刻到第一深度。 此后，保护性衬垫至少沉积在沟槽侧壁的上部。 保护性衬垫包括无机材料。 在至少一个第二蚀刻周期期间，将沟槽蚀刻到其最终深度。

公开(公告)号：US07112487B2

公开(公告)日：2006-09-26

申请号：US11079131

申请日：2005-03-14

Applicant: Martin Gutsche ,  Harald Seidl

Inventor： Martin Gutsche ,  Harald Seidl

IPC: H01L21/8242

CPC classification number: H01L27/10817 ,  H01L27/10814 ,  H01L27/10852 ,  H01L28/82

Abstract: The present invention provides a method for fabricating a stacked capacitor array (1), which comprises a regular arrangement of a plurality of stacked capacitors (2), with a stacked capacitor (2) being at a shorter distance from the respective adjacent stacked capacitor (2) in certain first directions (3) than in certain second directions (4), comprising the following method steps: provision of an auxiliary layer stack (5) having first auxiliary layers (6) with a predetermined etching rate and at least one second auxiliary layer (7) with a higher etching rate on a substrate (8); etching of in each case one hollow cylinder (9) for each stacked capacitor (2) through the auxiliary layer stack (5) in accordance with the regular arrangement, with the auxiliary layer stack (5) being left in place in intermediate regions (10) between the hollow cylinders (9); isotropic etching of the second auxiliary layers (7) to form widened portions (11) of the hollow cylinders (9), without any second auxiliary layer (7) being left in place between in each case two hollow cylinders (9) which adjoin one another in the first direction (3) and with a second residual auxiliary layer (7a) being left in place between in each case two hollow cylinders (9) which adjoin one another in the second direction (4); conformal deposition of an insulator layer (12) in order to completely fill the widened portions (11); deposition of a first electrode layer (13) in the hollow cylinders (9) in order to form the stacked capacitors (2); filling of the hollow cylinders (9) with a first filling (14); removal of the first auxiliary layers (6), the second residual auxiliary layers (7a) and the first filling (14) and completion of the stacked capacitor array (1).

公开(公告)号：US07087485B2

公开(公告)日：2006-08-08

申请号：US10765052

申请日：2004-01-28

Applicant: Harald Seidl ,  Martin Gutsche ,  Thomas Hecht

Inventor： Harald Seidl ,  Martin Gutsche ,  Thomas Hecht

IPC: H01L21/8242

CPC classification number: H01L21/3141 ,  H01L21/31116 ,  H01L27/1087

Abstract: A method for fabricating patterned ceramic layers on areas of a relief structure, wherein the layers may be arranged essentially perpendicular to a top side of a substrate. In exemplary embodiments, a patterned ceramic layer forms an oxide collar for a trench capacitor. The oxide collar is produced by a trench firstly being filled with a resist in its lower section, and an oxide layer subsequently being produced on the uncovered areas of the substrate with the aid of a low temperature ALD method. By means of anisotropic etching, only those portions of the ceramic layer which are arranged at the perpendicular walls of the trench remain. The resist filling may subsequently be removed, for example, by means of an oxygen plasma.

Abstract translation: 一种用于在浮雕结构的区域上制造图案化陶瓷层的方法，其中所述层可以布置成基本上垂直于衬底的顶侧。 在示例性实施例中，图案化陶瓷层形成用于沟槽电容器的氧化物环。 氧化物套环由首先在其下部填充有抗蚀剂的沟槽产生，随后在低温ALD方法的帮助下在衬底的未覆盖区域上产生氧化物层。 通过各向异性蚀刻，仅保留布置在沟槽的垂直壁处的陶瓷层的那些部分。 可以随后例如通过氧等离子体去除抗蚀剂填充。

公开(公告)号：US20050127421A1

公开(公告)日：2005-06-16

申请号：US10502930

申请日：2003-01-16

Applicant: Harald Seidl ,  Jorn Lutzen ,  Gerhard Beitel ,  Thomas Hecht ,  Annette Sanger ,  Albert Birner

Inventor： Harald Seidl ,  Jorn Lutzen ,  Gerhard Beitel ,  Thomas Hecht ,  Annette Sanger ,  Albert Birner

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/314 ,  H01L21/8242 ,  H01L29/51 ,  H01L27/108

CPC classification number: H01L21/28194 ,  H01L21/02175 ,  H01L21/02282 ,  H01L21/314 ,  H01L27/1085 ,  H01L27/10861 ,  H01L27/10873 ,  H01L28/40 ,  H01L29/517

Abstract: A semiconductor module is described which is essentially constructed from a silicon material and has an insulation layer for example in the form of a gate insulation layer or a MOS transistor or in the form of an insulation layer of a memory cell for a dynamic memory module. The insulation layer preferably comprises a dielectric material whose band gap is greater than the band gap of SiO2. To construct the insulation layer, use is made of materials which have a metal-fluorine compound, such as e.g. lithium fluoride. Particularly thin insulation layers are provided by the material described.

Abstract translation: 描述了一种半导体模块，其基本上由硅材料构成，并且具有例如栅极绝缘层或MOS晶体管形式的绝缘层，或以动态存储器模块的存储单元的绝缘层的形式。 绝缘层优选地包括其带隙大于SiO 2带隙的电介质材料。 为了构造绝缘层，使用具有金属 - 氟化合物的材料，例如， 氟化锂。 通过所述材料提供特别薄的绝缘层。

公开(公告)号：US20050090053A1

公开(公告)日：2005-04-28

申请号：US10501880

申请日：2003-01-08

Applicant: Dietmar Temmler ,  Martin Gutsche ,  Martin Popp ,  Harald Seidl

Inventor： Dietmar Temmler ,  Martin Gutsche ,  Martin Popp ,  Harald Seidl

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10867 ,  H01L27/10832 ,  H01L27/10864

Abstract: Memory cells having trench capacitors, the trench capacitor being at least partially filled with a material which could not withstand high-temperature processes used during the fabrication of a memory chip without impairment of its electrical parameters. What is essential to the invention is that the material of the trench capacitor is introduced into the trench after the high-temperature processes. The method according to the invention makes it possible to use dielectric layers having large dielectric constants and electrode layers made of metallic material. The electrical properties of the trench capacitor are thus improved in comparison with known trench capacitors.

Abstract translation: 具有沟槽电容器的存储单元，沟槽电容器至少部分地填充有不能承受在制造存储器芯片期间使用的高温处理而不损害其电参数的材料。 本发明的重要内容是在高温处理之后将沟槽电容器的材料引入沟槽。 根据本发明的方法使得可以使用具有大介电常数的电介质层和由金属材料制成的电极层。 与已知的沟槽电容器相比，沟槽电容器的电性能得到改善。

公开(公告)号：US20050067634A1

公开(公告)日：2005-03-31

申请号：US10950477

申请日：2004-09-28

Applicant: Cay-Uwe Pinnow ,  Martin Gutsche ,  Harald Seidl ,  Thomas Happ

Inventor： Cay-Uwe Pinnow ,  Martin Gutsche ,  Harald Seidl ,  Thomas Happ

IPC: G03G15/02 ,  H01L21/28 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC classification number: H01L21/28282 ,  H01L29/42332 ,  H01L29/7881 ,  Y10S438/954

Abstract: A nonvolatile integrated semiconductor memory has an arrangement of layers with a tunnel barrier layer and a charge-storing level. The charge-storing level has a dielectric material which stores scattered in charge carriers in a spatially fixed position. The tunnel barrier layer has a material through which high-energy charge carriers can tunnel. At least one interface surface of the charge-storing level has a greater microscopic roughness than the interface surface of the tunnel barrier layer, which is remote from the charge-storing level. The charge-storing level has a greater layer thickness in first regions than in second regions. This produces a relatively identical distribution and localization of positive and negative charge carriers in the lateral direction. The charge carriers which are scattered into the charge-storing level, therefore, recombine completely, so that the risk of unforeseen data loss during long-term operation of nonvolatile memories is reduced.

Abstract translation: 非易失性集成半导体存储器具有具有隧道势垒层和电荷存储电平的层的排列。 电荷储存电平具有在空间固定位置中分散存储在电荷载体中的电介质材料。 隧道势垒层具有高能电荷载流子穿过的材料。 电荷存储水平的至少一个界面表面具有比远离电荷存储水平的隧道势垒层的界面更大的微观粗糙度。 电荷存储水平在第一区域中具有比在第二区域中更大的层厚度。 这在横向方向产生正电荷载体和负电荷载体的相对相同的分布和定位。 因此，分散到电荷存储电平的电荷载体完全复合，从而降低了在非易失性存储器的长期操作期间不可预见的数据丢失的风险。

公开(公告)号：US06853023B2

公开(公告)日：2005-02-08

申请号：US10356780

申请日：2003-01-31

Applicant: Bernd Goebel ,  Jörn Lützen ,  Martin Popp ,  Harald Seidl

Inventor： Bernd Goebel ,  Jörn Lützen ,  Martin Popp ,  Harald Seidl

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10864

Abstract: A semiconductor memory cell configuration includes dynamic memory cells respectively having a trench capacitor and a vertical selection transistor, the memory cells being disposed in matrix form, the trench capacitors and the associated vertical selection transistors following one another in each case in the form of rows and/or columns.

Abstract translation: 半导体存储单元配置包括分别具有沟槽电容器和垂直选择晶体管的动态存储器单元，存储单元以矩阵形式布置，沟槽电容器和相关联的垂直选择晶体管在每种情况下彼此以行的形式相互依次， /或列。