公开(公告)号：US20050174262A1

公开(公告)日：2005-08-11

申请号：US11031529

申请日：2005-01-10

Applicant: Jun Lee ,  Joo-hyun Lee ,  Kyu-suk Lee ,  Jae-jin Lee

Inventor： Jun Lee ,  Joo-hyun Lee ,  Kyu-suk Lee ,  Jae-jin Lee

IPC: G11B20/10 ,  G11B20/14 ,  H03M5/14 ,  H03M7/00

CPC classification number: H03M5/145 ,  G11B20/1426 ,  G11B2020/1434 ,  G11B2020/1446

Abstract: Provided are a rate 13/15 MTR code encoding/decoding method and apparatus. The encoding method includes: generating a predetermined rate-13/15 MTR code in which 13-bit data corresponds to 15-bit data; outputting input 13-bit data as a 15-bit codeword according to the rate-13/15 MTR code; checking whether codewords satisfy a predetermined constraint condition by connecting the 15-bit codeword and a subsequent 15-bit codeword; and converting specific bits of the codewords if the codewords violate the constraint condition and not converting the codewords if the codewords do not violate the constraint condition. The rate-13/15 MTR (j=2, k=8) code includes: 8192 codewords obtained to prevent the number of consecutive transitions from becoming 3 at code boundaries in a modulation coding process. Data can be reliably reproduced with high write density, and a large amount of data can be stored in and reproduced from a magnetic recording information storage medium.

Abstract translation: 提供了一种速率13/15的MTR码编码/解码方法和装置。 编码方法包括：生成13比特数据对应于15比特数据的预定速率-13 / 15MTR码; 根据速率-13 / 15MTR码输出13位数据作为15位码字; 通过连接15位码字和随后的15位码字来检查码字是否满足预定约束条件; 以及如果所述码字违反所述约束条件并且如果所述码字不违反所述约束条件则不转换所述码字，则转换所述码字的特定比特。 速率-13 / 15MTR（j = 2，k = 8）码包括：8192个码字，用于防止在调制编码过程中在码边界处连续转换的数量变为3。 可以以高写入密度可靠地再现数据，并且可以将大量数据存储在磁记录信息存储介质中并从磁记录信息存储介质再现。

公开(公告)号：US06845050B2

公开(公告)日：2005-01-18

申请号：US10755732

申请日：2004-01-12

Applicant: Jae Jin Lee

Inventor： Jae Jin Lee

IPC: G11C11/407 ,  G11C5/14 ,  G11C7/00 ,  G11C7/06 ,  G11C7/10 ,  G11C7/22 ,  G11C11/408 ,  G11C11/409 ,  G11C11/00

CPC classification number: G11C7/106 ,  G11C5/14 ,  G11C7/06 ,  G11C7/1051 ,  G11C7/22

Abstract: A signal delay control circuit for use in a semiconductor memory device is disclosed. The circuit includes a first reference voltage generating unit for generating a first reference voltage; a second reference voltage generating unit for generating a second reference voltage that is lower than the first reference voltage; a control signal generating unit for generating a clock signal to drive input and output operations of internal circuits; and an impedance circuit in circuit with the first and second reference voltage generating units for generating a plurality of reference voltages to be applied to the internal circuits wherein the reference voltages are set in accordance with a distance between the control signal generating unit and the respective one of the internal circuits.

Abstract translation: 公开了一种用于半导体存储器件的信号延迟控制电路。 该电路包括用于产生第一参考电压的第一参考电压产生单元; 第二参考电压产生单元，用于产生低于第一参考电压的第二参考电压; 控制信号产生单元，用于产生用于驱动内部电路的输入和输出操作的时钟信号; 以及与第一和第二参考电压产生单元电路的电路中的阻抗电路，用于产生要施加到内部电路的多个参考电压，其中参考电压根据控制信号产生单元和相应的一个 的内部电路。

公开(公告)号：US06721211B2

公开(公告)日：2004-04-13

申请号：US10246083

申请日：2002-09-18

Applicant: Jae Jin Lee ,  Kang Seol Lee

Inventor： Jae Jin Lee ,  Kang Seol Lee

IPC: G11C700

CPC classification number: G11C7/1057 ,  G11C7/1051 ,  G11C11/4074 ,  G11C11/4096 ,  H02M3/07 ,  H02M2003/072

Abstract: A voltage generator for a semiconductor memory device that improves the drivability of an output driver by controlling a gate of the output driver to vary between an internal power supply voltage and a ground voltage, is disclosed. The voltage generator includes an output voltage controller to generate a pull-up signal for controlling a pull-up operation and a pull-down signal for controlling a pull-down operation, the pull-up signal having a level substantially equivalent to an internal power supply voltage if a cell plate voltage is higher than a cell plate reference voltage, and having a level below the cell plate voltage if the cell plate voltage is lower than the cell plate reference voltage. The voltage generator further includes an output driver to generate a stable cell plate voltage in response to the pull-up signal and the pull-down signal.

Abstract translation: 公开了一种用于半导体存储器件的电压发生器，其通过控制输出驱动器的栅极在内部电源电压和接地电压之间变化来提高输出驱动器的驱动能力。 电压发生器包括输出电压控制器以产生用于控制上拉操作的上拉信号和用于控制下拉操作的下拉信号，所述上拉信号的电平基本上等于内部功率 如果单元板电压高于单元板参考电压，并且如果单元板电压低于单元板参考电压，则具有低于单元板电压的电平的电源电压。 电压发生器还包括输出驱动器，以响应于上拉信号和下拉信号产生稳定的单元板电压。

公开(公告)号：US6057736A

公开(公告)日：2000-05-02

申请号：US135576

申请日：1998-08-18

Applicant: Min Gun Kim ,  Chang Seok Lee ,  Jae Jin Lee ,  Kwang Eui Pyun

Inventor： Min Gun Kim ,  Chang Seok Lee ,  Jae Jin Lee ,  Kwang Eui Pyun

IPC: H03G1/00 ,  H03F1/34 ,  H03G3/30

CPC classification number: H03F1/342 ,  H03G1/007 ,  H03F2200/151

Abstract: The present invention relates to a gain controlled amplifier, and more particularly, to a gain controlled amplifier using active feedback and variable resistance. It is an object of the present invention to provide a gain controlled amplifier minimizing the gain and the degradation of power characteristics generated when adjusting gain in a variable gain amplifier which receives signals having different power levels, amplifies them in accordance with each power level and outputs output signals in a constant power level. In order to achieve the above object, a gain controlled amplifier in accordance with the present invention comprises an amplifier and an active feedback means for negative feedbacking the output of the amplifier to the input of the amplifier, and further has a feedback amount controller inputting the controlled feedback signal to the amplifier by controlling the feedback amount of said active feedback means.

Abstract translation: 增益控制放大器本发明涉及一种增益控制放大器，更具体地说，涉及一种使用有源反馈和可变电阻的增益控制放大器。 本发明的一个目的是提供一种增益控制放大器，其最大程度地减小在接收具有不同功率电平的信号的可变增益放大器中调节增益时产生的功率特性的增益和劣化，根据每个功率电平放大它们 输出信号处于恒定功率电平。 为了实现上述目的，根据本发明的增益控制放大器包括放大器和用于将放大器的输出负反馈到放大器的输入的有源反馈装置，并且还具有反馈量控制器，其输入 通过控制所述主动反馈装置的反馈量来控制反馈信号到放大器。

公开(公告)号：US5914641A

公开(公告)日：1999-06-22

申请号：US907480

申请日：1997-08-11

Applicant: Kwang-Jun Yun ,  Chang-Seok Lee ,  Seong-Jae Maeng ,  Jae-Jin Lee

Inventor： Kwang-Jun Yun ,  Chang-Seok Lee ,  Seong-Jae Maeng ,  Jae-Jin Lee

IPC: H03F3/20 ,  H03F1/02 ,  H03F1/30 ,  H03F3/193 ,  H03G3/30 ,  H03F3/191

CPC classification number: H03F1/0272 ,  H03F1/301 ,  H03F3/1935 ,  H03G3/3042 ,  H03F2200/18 ,  H03F2200/318

Abstract: A gate voltage control circuit of a power amplifier for reducing the power dissipation by improving the efficiency at an average output power and for enhancing the linearity of the power amplifier at a maximum output power, the gate voltage control circuit comprising an input terminal for receiving an output power signal from a power amplifier; an output power detecting circuit for detecting the output power signal and for converting the detected output power signal to a DC voltage signal; a voltage dividing circuit comprising at least two resistors for dividing a voltage difference between the DC voltage signal and a negative voltage in a ratio of resistances of the resistors; and an output terminal for supplying the divided voltage as a gate voltage control signal.

Abstract translation: 一种功率放大器的栅极电压控制电路，用于通过提高平均输出功率的效率并以最大的输出功率来提高功率放大器的线性来降低功耗，所述栅极电压控制电路包括：输入端子，用于接收 来自功率放大器的输出功率信号; 输出功率检测电路，用于检测输出功率信号并将检测到的输出功率信号转换成DC电压信号; 分压电路，包括至少两个电阻器，用于以所述电阻器的电阻的比率分压所述直流电压信号和负电压之间的电压差; 以及用于将分压电压提供为栅极电压控制信号的输出端子。

公开(公告)号：US5901091A

公开(公告)日：1999-05-04

申请号：US63371

申请日：1998-04-21

Applicant: Jae Jin Lee

Inventor： Jae Jin Lee

IPC: G11C11/413 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G11C11/409 ,  G11C11/4096 ,  G11C11/417 ,  G11C16/04 ,  G11C7/02 ,  G11C8/00

CPC classification number: G11C7/1048 ,  G11C11/4096 ,  G11C7/1006 ,  G11C7/22

Abstract: There is disclosed a bidirectional data input/output circuit of a synchronous memory device and the method for controlling the same according to the present invention. The synchronous memory device according to the present invention is aimed at solving a data confusion problem generated when a write operation subsequent to a data read operation is performed in a data input/output line. Though the data line is a bidirectional bus data line by which an input/output is also performed, it can be applied to a circuit construction in which high and low potential data are inputted/outputted through an independent dedicated line. In addition, there is provided an internal buffer for inputting a write data into the memory device. The circuit according to the present invention further includes a memory for storing a data signal generated upon a read operation, when a read operation subsequent in time to a write operation is performed; and a device for selecting as a write data the opposite signal of the data signal generated upon a read operation when the two data lines both become active.

Abstract translation: 公开了根据本发明的同步存储器件的双向数据输入/输出电路及其控制方法。 根据本发明的同步存储装置旨在解决在数据输入/输出线中执行数据读取操作之后的写入操作时产生的数据混淆问题。 虽然数据线是还进行输入/输出的双向总线数据线，但是它可以应用于通过独立专用线输入/输出高电平和低电位数据的电路结构。 此外，提供了一种用于将写入数据输入到存储器件中的内部缓冲器。 根据本发明的电路还包括一个存储器，用于当执行写入操作的时间之后的读取操作时，存储在读取操作时产生的数据信号; 以及用于当两个数据线都变为活动时，在读取操作时产生的数据信号的相反信号作为写数据选择的装置。

公开(公告)号：US5862144A

公开(公告)日：1999-01-19

申请号：US956913

申请日：1997-10-23

Applicant: Chang Seok Lee ,  Ingab Hwang ,  Min Gun Kim ,  Jae Jin Lee ,  Kwang Eui Pyun

Inventor： Chang Seok Lee ,  Ingab Hwang ,  Min Gun Kim ,  Jae Jin Lee ,  Kwang Eui Pyun

IPC: G01R23/00 ,  G01R27/32 ,  G06F11/00

CPC classification number: G01R27/32

Abstract: A method for correcting a high frequency measurement error which can exactly correct the high frequency measurement error even with the use of a standard devices of which characteristic have not been verified by calculating the characteristic impedance of the correction device from the characteristics of an auxiliary measuring device calculated by using a general error correction method, and calculating again the once calculated characteristics of the auxiliary measuring device. The method in accordance with the present invention comprises the steps of modelling an auxiliary measuring device used for measuring a high frequency charateristics of the device under test by two transmission lines connected in series between two terminals and a parasitic component connected in parallel between a junction of the two transmission lines and a ground; and moving a reference measurement point to the junction of the two transmission lines by using a phase angle of each transmission line and calculating a reference impedance at the terminal of the auxiliary measuring device to which an object to be measured is connected by using the difference of the resultant reflection coefficients of each port.

Abstract translation: 一种用于校正高频测量误差的方法，即使使用通过从辅助测量装置的特性计算校正装置的特性阻抗尚未验证其特性的标准装置，也可以精确地校正高频测量误差 通过使用通用误差校正方法计算，并再次计算辅助测量装置的一次计算的特性。 根据本发明的方法包括以下步骤：对用于测量被测器件的高频特性的两个传输线串联连接在两个端子之间的辅助测量装置和在两个端子之间并联连接的寄生元件进行建模， 两条传输线和一条地面; 并且通过使用每个传输线的相位角将参考测量点移动到两个传输线的结点，并且通过使用所述差异来计算被测量对象的辅助测量装置的端子处的基准阻抗 每个端口的反射系数。

公开(公告)号：US5719810A

公开(公告)日：1998-02-17

申请号：US548212

申请日：1995-10-25

Applicant: Jae Jin Lee ,  Seung Han Ahn

Inventor： Jae Jin Lee ,  Seung Han Ahn

IPC: G06F11/00 ,  G11C7/00 ,  G11C7/10 ,  G11C29/38

CPC classification number: G06F11/004 ,  G11C29/38 ,  G11C7/00 ,  G11C7/1078

Abstract: A semiconductor memory device comprising a memory cell array for storing input data therein, a data output buffer for outputting the data stored in the memory cell array externally, an output terminal for transferring the output data from the data output buffer externally, a data input buffer for transferring the output data from the data output buffer to the memory cell array, a data register for temporarily storing the transferred data from the data input buffer, and a multiplexer connected among the memory cell array, the data register and the data output buffer, for selecting one of the data stored in the memory cell array and the data stored in the data register and transferring the selected data to the data output buffer. In the normal case, the multiplexer selects the data stored in the memory cell array and transfers the selected data to the data output buffer. In a specific case where the input data to the memory cell array have the same values or a regularity, the multiplexer selects the data stored in the data register and transfers the selected data to the data output buffer.

Abstract translation: 一种半导体存储器件，包括用于存储输入数据的存储单元阵列，用于将外部存储在存储单元阵列中的数据输出的数据输出缓冲器，用于从外部从数据输出缓冲器传送输出数据的输出端，数据输入缓冲器 用于将输出数据从数据输出缓冲器传送到存储单元阵列，用于临时存储来自数据输入缓冲器的传送数据的数据寄存器和连接在存储单元阵列，数据寄存器和数据输出缓冲器之间的多路复用器， 用于选择存储在存储单元阵列中的数据之一和存储在数据寄存器中的数据，并将所选择的数据传送到数据输出缓冲器。 在正常情况下，多路复用器选择存储在存储单元阵列中的数据，并将选择的数据传送到数据输出缓冲器。 在存储单元阵列的输入数据具有相同的值或规则性的特定情况下，多路复用器选择存储在数据寄存器中的数据并将选择的数据传送到数据输出缓冲器。

公开(公告)号：US5689396A

公开(公告)日：1997-11-18

申请号：US559605

申请日：1995-11-20

Applicant: Jae Jin Lee

Inventor： Jae Jin Lee

IPC: H01L27/04 ,  H01L27/02 ,  H03K17/00 ,  H03K17/04 ,  H03K17/08 ,  H03K19/003 ,  H03K19/0175 ,  H02H9/00

CPC classification number: H01L27/0266 ,  H03K19/00315

Abstract: A signal input unit for a semiconductor memory device comprising a signal input terminal, an electrostatic discharge protection circuit for discharging an electrostatic signal of high level from the input terminal to a ground voltage source, a signal transfer circuit connected in parallel to the electrostatic discharge protection circuit, for switching a normal input signal from the input terminal, a signal transfer control circuit for controlling a switching operation of the signal transfer circuit, and a signal input circuit for buffering an output signal from the electrostatic discharge protection circuit or the signal transfer circuit and transferring the buffered signal to an internal circuit of the semiconductor memory device. The electrostatic discharge protection circuit sufficiently discharges the external electrostatic signal to the ground voltage source in a standby mode of the semiconductor memory device. The signal transfer circuit is connected in parallel to the electrostatic discharge protection circuit so that the normal input signal can be transferred directly to the signal input circuit in an operation mode of the semiconductor memory device with no delay by the electrostatic discharge protection circuit. Therefore, a signal delay can be prevented.

Abstract translation: 一种用于半导体存储器件的信号输入单元，包括信号输入端子，用于将高电平的静电信号从输入端子放电到地电压源的静电放电保护电路，与静电放电保护并联连接的信号传输电路 电路，用于切换来自输入端子的正常输入信号，用于控制信号传送电路的切换操作的信号传送控制电路，以及用于缓冲来自静电放电保护电路或信号传输电路的输出信号的信号输入电路 以及将缓冲信号传送到半导体存储器件的内部电路。 在半导体存储器件的待机模式下，静电放电保护电路将外部静电信号充分地放电到地电压源。 信号传送电路并联连接到静电放电保护电路，使得在半导体存储器件的操作模式下，通过静电放电保护电路不会将正常输入信号直接传送到信号输入电路。 因此，可以防止信号延迟。

公开(公告)号：US09893562B2

公开(公告)日：2018-02-13

申请号：US14949100

申请日：2015-11-23

Applicant: Jae Jin Lee ,  Kyo Beum Lee

Inventor： Jae Jin Lee ,  Kyo Beum Lee

IPC: H02J9/06 ,  H05B37/00 ,  H02J7/00

CPC classification number: H02J9/061 ,  H02J7/0029 ,  H02J2007/004 ,  H05B33/0815 ,  H05B33/0842 ,  H05B37/00 ,  H05B37/0227

Abstract: Disclosed herein is a direct current (DC) uninterruptible power supply system. The DC uninterruptible power supply system is connected to a DC power conversion system converting prevailing alternating current (AC) power into DC power, supplies the DC power to a load, charges an internal auxiliary power supply device with the DC power, and continuously supplies power to the load from the auxiliary power supply device while cutting off an electric connection with the DC power conversion system when the DC power conversion system short-circuits due to a leakage current or damage thereof or is disconnected.