公开(公告)号：US06714038B2

公开(公告)日：2004-03-30

申请号：US10171717

申请日：2002-06-14

Applicant: Byong-Kwon Lee ,  Kwang-Jin Lee

Inventor： Byong-Kwon Lee ,  Kwang-Jin Lee

IPC: H03K1900

CPC classification number: G11C7/109 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1084 ,  G11C29/14 ,  G11C29/48

Abstract: An apparatus and method for controlling an input termination of a semiconductor memory device that easily detect and analyze defects, functions and reliability of the device by controlling operations of the input termination. The apparatus comprises an input termination circuit for matching an impedance of a transmission line, a control circuit for processing test commands and outputting control signals in response to said processing, and a switching circuit for selectively turning on/off the input termination circuit in response to the control signals output from the control circuit.

Abstract translation: 一种用于控制半导体存储器件的输入端接的装置和方法，其通过控制输入端子的操作来容易地检测和分析器件的缺陷，功能和可靠性。 该装置包括用于匹配传输线路的阻抗的输入终端电路，用于处理测试命令的控制电路并响应于所述处理输出控制信号;以及切换电路，用于响应于所述输入终端电路选择性地接通/ 控制信号从控制电路输出。

公开(公告)号：US06459652B1

公开(公告)日：2002-10-01

申请号：US09996225

申请日：2001-11-28

Applicant: Jong Cheol Lee ,  Kwang Jin Lee

Inventor： Jong Cheol Lee ,  Kwang Jin Lee

IPC: G11C800

CPC classification number: G11C7/1066 ,  G11C7/1051 ,  G11C7/22 ,  G11C29/14

Abstract: A semiconductor memory device effectively capable of removing skew between data output of a data output circuit and an echo clock of an echo clock generator is provided. The semiconductor memory device comprises a delay circuit comprising a plurality of delay paths for delaying the data enable clock by different time, a test controller for generating a mode select signal and a delay path test signal in response to a test code signal, and a delay signal selection circuit comprising a plurality of fuses for producing a default delay path select signal based on a programmed state of the plurality of fuses, and a multiplexer, responsive to the mode select signal, for selectively providing the default delay path select signal or the delay path test signal to the delay circuit.

Abstract translation: 提供了有效地消除数据输出电路的数据输出与回波时钟发生器的回波时钟之间的偏差的半导体存储器件。 半导体存储器件包括延迟电路，该延迟电路包括多个用于将数据使能时钟延迟不同时间的延迟路径，用于响应于测试代码信号产生模式选择信号和延迟路径测试信号的测试控制器以及延迟 信号选择电路，包括多个保险丝，用于基于多个保险丝的编程状态产生默认延迟路径选择信号;以及复用器，响应于模式选择信号，用于选择性地提供默认延迟路径选择信号或延迟 路径测试信号到延迟电路。

公开(公告)号：US10052591B2

公开(公告)日：2018-08-21

申请号：US13876334

申请日：2011-09-27

Applicant: Kwang-Jin Lee ,  Ah Reum Lee ,  Yong-Cheol Shin ,  Joon Yul Yang

Inventor： Kwang-Jin Lee ,  Ah Reum Lee ,  Yong-Cheol Shin ,  Joon Yul Yang

IPC: B01D65/08 ,  B01D65/02

CPC classification number: B01D65/02 ,  B01D65/08 ,  B01D2313/26 ,  B01D2315/06 ,  B01D2321/185

Abstract: Disclosed are system and method for filtration which can minimize the contamination of the filtering membrane through a pretreatment and perform the pretreatment and the filtration with a filtering membrane in a single filtering unit so that any need for separate and additional space and facility for the pretreatment can be obviated. The system for filtration of the present invention comprises a fine bubble supplier for providing fine bubbles into the feed water. The pretreatment is performed by supplying the feed water to be treated into the filtering unit through a dynamic filtration layer which is formed in the filtering unit as the fine bubbles rise.

公开(公告)号：US20140191443A1

公开(公告)日：2014-07-10

申请号：US14233424

申请日：2011-12-09

Applicant: Hyun Kuk Park ,  Ik Hyun Oh ,  Hee Jun Yoon ,  Hyeon Taek Son ,  Kwang Jin Lee ,  Hee Seon Bang ,  Han Sur Bang

Inventor： Hyun Kuk Park ,  Ik Hyun Oh ,  Hee Jun Yoon ,  Hyeon Taek Son ,  Kwang Jin Lee ,  Hee Seon Bang ,  Han Sur Bang

IPC: C04B35/64 ,  C04B35/56 ,  B23K20/12

CPC classification number: C04B35/64 ,  B22F3/105 ,  B23K20/1245 ,  C04B35/5626 ,  C04B35/645 ,  C04B2235/6562 ,  C04B2235/6581 ,  C04B2235/666 ,  C04B2235/77 ,  C04B2235/96 ,  C22C29/08

Abstract: The present invention relates to a preparation method of a tungsten carbide sintered body for a friction stir welding tool used in a friction stir welding tool of a high melting point material such as steel, titanium and the like or a dissimilar material such as aluminum, magnesium-steel, titanium and the like using pulsed current activation through a discharge plasma sintering apparatus. The preparation method comprises the following steps: filling a tungsten carbide (WC) powder in a mold made of a graphite material; mounting the mold filled with tungsten carbide powder in a chamber of a discharge plasma sintering apparatus; making a vacuum inside of the chamber; molding the tungsten carbide powder while maintaining a constant pressure inside the mold and increasing the temperature according to a set heat increase pattern until the temperature reaches a final target temperature; and cooling the inside of the chamber while maintaining the pressure pressurized in the mold after the molding step. According to the preparation method of a tungsten carbide sintered body for a friction stir welding tool, it is possible to obtain a high relative density of 99.5% or higher, and to prepare a uniform sintered body having a homogeneous tissue with little particle growth, high toughness, high abrasion resistance and high strength within a short time by a single process when preparing a tungsten carbide sintered body appropriate for a friction stir welding tool by using pulsed current activation through a discharge plasma sintering apparatus. In addition, since a sintered body is prepared with only a tungsten carbide single material, excluding a sintering additive such as cobalt, a preparation method is simplified, preparation costs are reduced, and toughness, abrasion resistance and strength are superior compared with a sintered body containing cobalt, a sintering additive.

Abstract translation: 本发明涉及一种用于摩擦搅拌焊接工具的碳化钨烧结体的制备方法，该工具用于诸如钢，钛等的高熔点材料的摩擦搅拌焊接工具或诸如铝，镁之类的异种材料 钢，钛等，通过放电等离子体烧结装置进行脉冲电流激活。 该制备方法包括以下步骤：在由石墨材料制成的模具中填充碳化钨（WC）粉末; 将填充有碳化钨粉末的模具安装在放电等离子体烧结装置的腔室中; 在室内进行真空; 在模具内保持恒定压力的同时成型碳化钨粉末，并根据设定的热量增加模式增加温度，直到温度达到最终目标温度; 并且在模制步骤之后保持在模具中加压的压力同时冷却腔室的内部。 根据用于摩擦搅拌焊接工具的碳化钨烧结体的制备方法，可以获得99.5％以上的高相对密度，并且制备均匀的具有少量颗粒生长的均匀组织的烧结体，高 当通过使用脉冲电流激活通过放电等离子体烧结装置制备适用于摩擦搅拌焊接工具的碳化钨烧结体时，通过单一工艺在短时间内具有韧性，高耐磨性和高强度。 此外，由于仅使用碳化钨单一材料制成烧结体，不包括钴等烧结添加剂，因此制备方法简单，制备成本降低，韧性，耐磨耗性和强度高于烧结体 含钴，烧结添加剂。

公开(公告)号：US08588010B2

公开(公告)日：2013-11-19

申请号：US12929349

申请日：2011-01-18

Applicant: Kwang Jin Lee ,  Du Eung Kim ,  Hye Jin Kim

Inventor： Kwang Jin Lee ,  Du Eung Kim ,  Hye Jin Kim

IPC: G11C7/22

CPC classification number: G11C13/0064 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/56 ,  G11C11/5628 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C15/00 ,  G11C2013/0078 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2211/5643

Abstract: At least one embodiment includes a non-volatile memory cell array, a write buffer configured to store data being written into the non-volatile memory cell array, and a write unit configured to write data into the non-volatile memory cell array. The write unit is configured to perform writing of data such that each data will have reached a stable storage state in the non-volatile memory prior to being over-written in the write buffer.

公开(公告)号：US08320168B2

公开(公告)日：2012-11-27

申请号：US13108143

申请日：2011-05-16

Applicant: Hye-jin Kim ,  Kwang-jin Lee ,  Du-eung Kim

Inventor： Hye-jin Kim ,  Kwang-jin Lee ,  Du-eung Kim

IPC: G11C11/00

CPC classification number: G11C13/0064 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0092

Abstract: A method of operating a phase change random access memory (PRAM) device includes performing a program operation to store data in selected PRAM cells of the device, wherein the program operation comprises a plurality of sequential program loops. The method further comprises suspending the program operation in the middle of the program operation, and after suspending the program operation, resuming the program operation in response to a resume command.

Abstract translation: 操作相变随机存取存储器（PRAM）装置的方法包括执行程序操作以将数据存储在所述装置的所选PRAM单元中，其中所述程序操作包括多个顺序程序循环。 该方法还包括在编程操作的中间暂停编程操作，并且在暂停编程操作之后，响应于恢复命令恢复程序操作。

公开(公告)号：US08248860B2

公开(公告)日：2012-08-21

申请号：US12659840

申请日：2010-03-23

Applicant: Kwang-Jin Lee ,  Chang-Soo Lee ,  Joon-Min Park ,  Hui-Kwon Seo ,  Qi Wang

Inventor： Kwang-Jin Lee ,  Chang-Soo Lee ,  Joon-Min Park ,  Hui-Kwon Seo ,  Qi Wang

IPC: G11C16/04

CPC classification number: G11C13/0097 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0088 ,  G11C2211/5646

Abstract: A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.

Abstract translation: 存储器件包括存储单元阵列，该存储单元阵列包括多个存储器块，每个存储器块包括多个存储器单元，耦合到多个存储器单元中的行的多个字线，耦合到多个存储器单元的列的多个位线 多个存储单元，以及控制擦除操作的控制单元，使得擦除数据被同时写入与擦除单元对应的多个存储单元中。 第一擦除模式可以包括第一擦除单元和第一擦除数据模式。 第二擦除模式可以包括第二擦除单元和第二擦除模式。 第一和第二擦除单元以及第一和第二擦除数据模式中的至少一个是不同的。

公开(公告)号：US08223527B2

公开(公告)日：2012-07-17

申请号：US12289937

申请日：2008-11-07

Applicant: Kwang Jin Lee ,  Qi Wang ,  Beak Hyung Cho

Inventor： Kwang Jin Lee ,  Qi Wang ,  Beak Hyung Cho

IPC: G11C7/00 ,  G11C11/00

CPC classification number: G11C7/1078 ,  G11C7/1096 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2213/72

Abstract: In one embodiment, the semiconductor device, includes a non-volatile memory cell array, and a control unit configured to generate a mode signal indicating if a flash mode has been enabled. A write circuit is configured to write in the non-volatile memory cell array based on the mode signal such that the write circuit disables erasing the non-volatile memory cell array if the flash mode has not been enabled and instructions to erase one or more cells of the non-volatile memory cell array is received.

Abstract translation: 在一个实施例中，半导体器件包括非易失性存储单元阵列，以及控制单元，被配置为产生指示闪光模式是否被使能的模式信号。 写电路被配置为基于模式信号写入非易失性存储单元阵列，使得如果闪存模式尚未被使能，则写电路禁止擦除非易失性存储单元阵列，并且指令擦除一个或多个单元 接收非易失性存储单元阵列。

公开(公告)号：US08194447B2

公开(公告)日：2012-06-05

申请号：US12314513

申请日：2008-12-11

Applicant: Hye-Jin Kim ,  Kwang-Jin Lee ,  Du-Eung Kim ,  Hung-Jun An

Inventor： Hye-Jin Kim ,  Kwang-Jin Lee ,  Du-Eung Kim ,  Hung-Jun An

IPC: G11C16/04

CPC classification number: G11C7/1078 ,  G11C5/14 ,  G11C7/1096 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/72

Abstract: A non-volatile memory device using a variable resistive element includes a memory cell array having a plurality of non-volatile memory cells, a first voltage generator generating a first voltage, a voltage pad receiving an external voltage that has a level higher than the first voltage, a sense amplifier supplied with the first voltage and reading data from the non-volatile memory cells selected from the memory cell array, and a write driver supplied with the external voltage and writing data to the non-volatile memory cells selected from the memory cell array.

Abstract translation: 使用可变电阻元件的非易失性存储器件包括具有多个非易失性存储器单元的存储单元阵列，产生第一电压的第一电压发生器，接收高于第一电压的电平的外部电压的电压焊盘 电压，提供有第一电压的读出放大器和从存储单元阵列中选择的非易失性存储器单元读取数据，以及提供有外部电压的写入驱动器，并将数据写入从存储器中选择的非易失性存储器单元 单元格阵列。

公开(公告)号：US08139432B2

公开(公告)日：2012-03-20

申请号：US12901168

申请日：2010-10-08

Applicant: Byung-gil Choi ,  Beak-hyung Cho ,  Jun-Soo Bae ,  Kwang-Jin Lee

Inventor： Byung-gil Choi ,  Beak-hyung Cho ,  Jun-Soo Bae ,  Kwang-Jin Lee

IPC: G11C7/04

CPC classification number: G11C7/18 ,  G11C7/04 ,  G11C8/12 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2029/2602 ,  H01L27/24

Abstract: A nonvolatile memory device comprising: a plurality of memory banks, each of which operates independently and includes a plurality of resistance memory cells, each cell including a variable resistive element having a resistance varying depending on stored data; a plurality of global bit lines, each global bit line being shared by the plurality of memory banks; a temperature compensation circuit including one or more reference cells; and a data read circuit which is electrically connected to the plurality of global bit lines and performs a read operation by supplying at least one of the resistance memory cells with a current varying according to resistances of the reference cells.

Abstract translation: 一种非易失性存储器件，包括：多个存储体，每个存储体各自独立地操作并且包括多个电阻存储器单元，每个单元包括具有根据存储的数据而变化的电阻的可变电阻元件; 多个全局位线，每个全局位线由多个存储体共享; 包括一个或多个参考单元的温度补偿电路; 以及数据读取电路，其电连接到所述多个全局位线，并且通过向所述电阻存储单元中的至少一个提供根据所述参考单元的电阻而变化的电流来执行读取操作。