公开(公告)号：US20140337604A1

公开(公告)日：2014-11-13

申请号：US13890654

申请日：2013-05-09

Applicant: Beeman C. Strong ,  Matthew C. Merten ,  Tong Li

Inventor： Beeman C. Strong ,  Matthew C. Merten ,  Tong Li

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/3806 ,  G06F9/3857 ,  G06F11/3476 ,  G06F11/3636

Abstract: A processing device implementing minimizing bandwidth to track return targets by an instruction tracing system is disclosed. A processing device of the disclosure an instruction fetch unit comprising a return stack buffer (RSB) to predict a target address of a return (RET) instruction corresponding to a call (CALL) instruction. The processing device further includes a retirement unit comprising an instruction tracing module to initiate instruction tracing for instructions executed by the processing device, determine whether the target address of the RET instruction was mispredicted, determine a value of call depth counter (CDC) maintained by the instruction tracing module, and when the target address of the RET instruction was not mispredicted and when the value of the CDC is greater than zero, generate an indication that the RET instruction branches to a next linear instruction after the corresponding CALL instruction.

Abstract translation: 公开了一种通过指令跟踪系统实现最小化带宽以跟踪返回目标的处理设备。 本公开的处理装置包括一个指令提取单元，该单元包括用于预测与一个调用（CALL）指令相对应的返回（RET）指令的目标地址的返回栈缓冲器（RSB）。 所述处理装置还包括退出单元，所述退出单元包括指令跟踪模块，用于启动由所述处理设备执行的指令的指令跟踪，确定所述RET指令的目标地址是否被错误预测，确定由所述处理设备维护的所述呼叫深度计数器 指令跟踪模块，并且当RET指令的目标地址未被错误预测时，并且当CDC的值大于零时，生成指令在相应的CALL指令之后分支到下一个线性指令。

公开(公告)号：US20140201505A1

公开(公告)日：2014-07-17

申请号：US13997837

申请日：2012-03-30

Applicant: Matthew C. Merten ,  Tong Li ,  Vijaykumar B. Kadgi ,  Srikanth T. Srinivasan ,  Christine E. Wang

Inventor： Matthew C. Merten ,  Tong Li ,  Vijaykumar B. Kadgi ,  Srikanth T. Srinivasan ,  Christine E. Wang

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/3851 ,  G06F9/4843 ,  Y02D10/24

Abstract: A processor includes one or more execution units to execute instructions of a plurality of threads and thread control logic coupled to the execution units to predict whether a first of the plurality of threads is ready for selection in a current cycle based on readiness of instructions of the first thread in one or more previous cycles, to predict whether a second of the plurality of threads is ready for selection in the current cycle based on readiness of instructions of the second thread in the one or more previous cycles, and to select one of the first and second threads in the current cycle based on the predictions.

Abstract translation: 处理器包括一个或多个执行单元，用于执行多个线程的指令和与执行单元耦合的线程控制逻辑，以基于当前周期的指令的准备就绪来预测多个线程中的第一个线程是否准备好在当前周期中进行选择 在一个或多个先前循环中的第一线程，以基于所述一个或多个先前循环中的第二线程的指令的准备来预测多个线程中的第二线程是否准备好在当前周期中进行选择，并且选择 基于预测的当前循环中的第一和第二个线程。

公开(公告)号：US20140095838A1

公开(公告)日：2014-04-03

申请号：US13631664

申请日：2012-09-28

Applicant: VIJAYKUMAR VIJAY KADGI ,  JAMES D. HADLEY ,  AVINASH SODANI ,  MATTHEW C. MERTEN ,  MORRIS MARDEN ,  JOSEPH A. MCMAHON ,  GRACE C. LEE ,  LAURA A. KNAUTH ,  ROBERT S. CHAPPELL ,  FARIBORZ TABESH

Inventor： VIJAYKUMAR VIJAY KADGI ,  JAMES D. HADLEY ,  AVINASH SODANI ,  MATTHEW C. MERTEN ,  MORRIS MARDEN ,  JOSEPH A. MCMAHON ,  GRACE C. LEE ,  LAURA A. KNAUTH ,  ROBERT S. CHAPPELL ,  FARIBORZ TABESH

IPC: G06F9/30

CPC classification number: G06F9/30105 ,  G06F9/384

Abstract: A processor includes a processing unit including a storage module having stored thereon a physical reference list for storing identifications of physical registers that have been referenced by multiple logical registers, and a reclamation module for reclaiming physical registers to a free list based on a count of each of the physical registers on the physical reference list.

Abstract translation: 处理器包括处理单元，该处理单元包括存储有存储有多个逻辑寄存器所引用的物理寄存器的标识的物理参考列表的存储模块，以及用于基于每个 的物理寄存器在物理参考列表中。

公开(公告)号：US08607241B2

公开(公告)日：2013-12-10

申请号：US10880638

申请日：2004-06-30

Applicant: Bratin Saha ,  Matthew C. Merten ,  Per Hammarlund

Inventor： Bratin Saha ,  Matthew C. Merten ,  Per Hammarlund

IPC: G06F9/46 ,  G06F9/30 ,  G06F9/40 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44

CPC classification number: G06F9/30021 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3857 ,  G06F9/526 ,  G06F2209/521

Abstract: A method, apparatus, and system are provided for performing compare and exchange operations using a sleep-wakeup mechanism. According to one embodiment, an instruction at a processor is executed to help acquire a lock on behalf of the processor. If the lock is unavailable to be acquired by the processor, the instruction is put to sleep until an event has occurred.

Abstract translation: 提供了一种使用睡眠 - 唤醒机制​​执行比较和交换操作的方法，装置和系统。 根据一个实施例，执行处理器处的指令以帮助代表处理器获取锁定。 如果锁不能由处理器获取，则指令将进入休眠状态，直到发生事件为止。

公开(公告)号：US08291196B2

公开(公告)日：2012-10-16

申请号：US11323037

申请日：2005-12-29

Applicant: Stephan J. Jourdan ,  Matthew C. Merten ,  Alexandre J. Farcy

Inventor： Stephan J. Jourdan ,  Matthew C. Merten ,  Alexandre J. Farcy

IPC: G06F9/00

CPC classification number: G06F9/3832 ,  G06F9/3838

Abstract: Apparatuses and methods for dead instruction identification are disclosed. In one embodiment, an apparatus includes an instruction buffer and a dead instruction identifier. The instruction buffer is to store an instruction stream having a single entry point and a single exit point. The dead instruction identifier is to identify dead instructions based on a forward pass through the instruction stream.

Abstract translation: 公开了用于死指示识别的装置和方法。 在一个实施例中，一种装置包括指令缓冲器和死指令标识符。 指令缓冲器用于存储具有单个入口点和单个出口点的指令流。 死指令标识符是基于通过指令流的向前传递来识别死指令。

公开(公告)号：US09652236B2

公开(公告)日：2017-05-16

申请号：US14139263

申请日：2013-12-23

Applicant: Srikanth T. Srinivasan ,  Mark J. Dechene ,  Yury N. Ilin ,  Justin M. Deinlein ,  Christine E. Wang ,  Matthew C. Merten

Inventor： Srikanth T. Srinivasan ,  Mark J. Dechene ,  Yury N. Ilin ,  Justin M. Deinlein ,  Christine E. Wang ,  Matthew C. Merten

IPC: G06F9/26 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30109 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3877 ,  G06F9/3885

Abstract: A processor includes a logic to execute a first instruction and a second instruction. The first instruction is ordered before the second instruction. Each instruction references a respective logical register assigned to a respective physical register. The processor also includes logic to reassign a physical register of the second instruction to another logical register before retirement of the first instruction.

公开(公告)号：US09582275B2

公开(公告)日：2017-02-28

申请号：US13118766

申请日：2011-05-31

Applicant: Michael W. Chynoweth ,  Peggy J. Irelan ,  Matthew C. Merten ,  Seung-Woo Kim ,  Laura A. Knauth ,  Stanislav Bratanov

Inventor： Michael W. Chynoweth ,  Peggy J. Irelan ,  Matthew C. Merten ,  Seung-Woo Kim ,  Laura A. Knauth ,  Stanislav Bratanov

IPC: G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F9/30 ,  G06F11/34

CPC classification number: G06F9/30058 ,  G06F9/30054 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/3016 ,  G06F11/3409 ,  G06F11/3476 ,  G06F11/348 ,  G06F12/0875

Abstract: In one embodiment, a processor includes a performance monitor including a last branch record (LBR) stack to store a call stack to an event of interest, where the call stack is collected responsive to a trigger for the event. The processor further includes logic to control the LBR stack to operate in a call stack mode such that an entry to a call instruction for a leaf function is cleared on return from the leaf function. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括性能监视器，其包括最后一个分支记录（LBR）堆栈，以将呼叫堆栈存储到感兴趣的事件，响应于该事件的触发来收集呼叫栈。 处理器还包括控制LBR堆栈以调用堆栈模式操作的逻辑，使得从叶片功能返回时清除叶子功能的调用指令的条目。 描述和要求保护其他实施例。

公开(公告)号：US09092214B2

公开(公告)日：2015-07-28

申请号：US13434564

申请日：2012-03-29

Applicant: Laura A. Knauth ,  Matthew C. Merten ,  Ronak Singhal ,  Hugh M. Caffey

Inventor： Laura A. Knauth ,  Matthew C. Merten ,  Ronak Singhal ,  Hugh M. Caffey

IPC: G06F15/80 ,  G06F9/30 ,  G06F11/34

CPC classification number: G06F9/3013 ,  G06F9/30109 ,  G06F9/30112 ,  G06F11/3409 ,  G06F11/3466 ,  G06F2201/88

Abstract: A processor includes an execution unit to execute instructions, where each operand of each executed instruction has one or more elements of an element size and at least one operand of the instruction corresponds to a register of a register size. The processor further includes a counter configured to count a number of instructions that have been executed by the execution unit associated with a particular combination of register size and element size.

Abstract translation: 处理器包括执行指令的执行单元，其中每个执行指令的每个操作数具有元素大小的一个或多个元素，并且指令的至少一个操作数对应于寄存器大小的寄存器。 处理器还包括计数器，其被配置为对由执行单元执行的与寄存器大小和元素大小的特定组合相关联的指令数进行计数。

公开(公告)号：US20150006496A1

公开(公告)日：2015-01-01

申请号：US13931860

申请日：2013-06-29

Applicant: Ravi RAJWAR ,  Matthew C. MERTEN ,  Christine E. WANG ,  Vijaykumar B. KADGI ,  Rajesh S. PARTHASARATHY

Inventor： Ravi RAJWAR ,  Matthew C. MERTEN ,  Christine E. WANG ,  Vijaykumar B. KADGI ,  Rajesh S. PARTHASARATHY

IPC: G06F9/46

CPC classification number: G06F9/467 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3863 ,  G06F9/466 ,  G06F9/528

Abstract: A processor, system, and method are described for continued retirement of operations during a commit of a speculative region of program code. For example, one embodiment of a method comprises the operations of identifying a plurality of transactional memory regions in program code, including a first transactional memory region; and retiring one or more of a plurality of operations which follow the first transactional memory region even when a commit operation associated with the first transactional memory region is waiting to complete.

Abstract translation: 描述了处理器，系统和方法，用于在提交程序代码的推测区域期间继续退出操作。 例如，方法的一个实施例包括在程序代码中识别多个事务存储区域的操作，包括第一事务存储器区域; 以及即使当与第一事务存储器区域相关联的提交操作等待完成时，退出遵循第一事务存储器区域的多个操作中的一个或多个操作。

公开(公告)号：US20140156977A1

公开(公告)日：2014-06-05

申请号：US13994699

申请日：2011-12-28

Applicant: Mark J. Dechene ,  Matthew C. Merten ,  Sean P. Mirkes

Inventor： Mark J. Dechene ,  Matthew C. Merten ,  Sean P. Mirkes

IPC: G06F9/38

CPC classification number: G06F9/3861 ,  G06F9/3844 ,  G06F9/3851 ,  G06F9/3885

Abstract: Techniques are described for enabling and/or disabling a secondary jump execution unit (JEU) in a micro-processor. The secondary JEU is incorporated in the micro-processor to operate concurrently with a primary JEU, and to enable the handling of simultaneous branch mispredicts on multiple branches. Activation and deactivation of the secondary JEU may be controlled by a pressure counter or a confidence counter. A pressure counter mechanism increments a count for each branch operation executed within the processor and decrements the count by a decay value during each cycle. A confidence counter mechanism increments a count for each correctly predicted branch, and decrements the count for each mispredict. Each counter signals an activation component, such as a port binding hardware component, to begin binding micro-operations to the secondary JEU when the counter exceeds an activation threshold. The counter mechanism may be thread-agnostic or thread-specific.

Abstract translation: 描述了在微处理器中启用和/或禁用辅助跳转执行单元（JEU）的技术。 次级JEU被并入微处理器以与主JEU同时操作，并且能够在多个分支上处理同时的分支错误预测。 次级JEU的激活和停用可以由压力计数器或置信计数器来控制。 压力计数器机构增加在处理器内执行的每个分支操作的计数，并在每个周期期间将计数减去衰减值。 置信度计数机制增加每个正确预测分支的计数，并减少每个错误预测的计数。 当计数器超过激活阈值时，每个计数器发出一个激活组件，例如端口绑定硬件组件，开始将微操作绑定到辅助JEU。 计数器机制可能是线程不可知或线程特定的。