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公开(公告)号：US08479062B2
公开(公告)日：2013-07-02
申请号：US12959993
申请日：2010-12-03
IPC分类号： G11C29/00
CPC分类号： G06F11/1048
摘要： Program disturb error logging and correction for a flash memory including a computer implemented method for storing data. The method includes receiving a write request that includes data and a write address of a target page in a memory. A previously programmed page at a specified offset from the target page is read from the memory. Contents of the previously programmed page are compared to an expected value of the previously programmed page. Error data is stored in an error log in response to contents of the previously programmed page being different than the expected value of the previously programmed page, the error data describing an error in the previously programmed page and the error data used by a next read operation to the previously programmed page to correct the error in the previously programmed page. The received data is written to the target page in the memory.
摘要翻译： 用于闪存的程序干扰错误记录和校正，包括用于存储数据的计算机实现的方法。 该方法包括在存储器中接收包括目标页面的数据和写入地址的写入请求。 从存储器中读取与目标页面指定偏移的先前编程的页面。 将先前编程的页面的内容与先前编程的页面的预期值进行比较。 响应于先前编程的页面的内容与先前编程的页面的期望值不同的错误数据存储在错误日志中，描述先前编程的页面中的错误的错误数据和下一个读取操作使用的错误数据 到先前编程的页面，以纠正以前编程的页面中的错误。 接收的数据被写入存储器中的目标页面。
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公开(公告)号：US20130166822A1
公开(公告)日：2013-06-27
申请号：US13336385
申请日：2011-12-23
CPC分类号： G06F3/0688 , G06F3/0601 , G06F3/061 , G06F3/0619 , G06F3/064 , G06F3/0652 , G06F12/0246 , G06F2212/7201 , G06F2212/7211
摘要： Solid-state storage management for a system that includes a main board and a solid-state storage board separate from the main board is provided. The sold-state storage board includes a solid-state memory device and solid-state storage devices. The system is configured to perform a method that includes a correspondence being established, by a software module located on the main board, between a first logical address and a first physical address on the solid-state storage devices. The correspondence between the first logical address and the first physical address is stored in a location on the solid-state memory device. The method also includes translating the first logical address into the first physical address. The translating is performed by an address translator module located on the solid-state storage board and is based on the previously established correspondence between the first logical address and the first physical address.
摘要翻译： 提供了一种包含与主板分离的主板和固态存储板的系统的固态存储管理。 销售状态存储板包括固态存储器件和固态存储器件。 该系统被配置为执行包括通过位于主板上的软件模块在固态存储设备上的第一逻辑地址和第一物理地址之间建立的对应关系的方法。 第一逻辑地址和第一物理地址之间的对应关系被存储在固态存储器件的一个位置。 该方法还包括将第一逻辑地址转换为第一物理地址。 翻译由位于固态存储板上的地址转换器模块执行，并且基于先前建立的第一逻辑地址和第一物理地址之间的对应关系。
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公开(公告)号：US20130011993A1
公开(公告)日：2013-01-10
申请号：US13619493
申请日：2012-09-14
IPC分类号： H01L21/02
CPC分类号： G11C8/10 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0083 , H01L27/2463 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/1675
摘要： A method of manufacturing a phase change memory cell on a substrate. The method includes: etching a first trench in the substrate; depositing a first conductor layer in the first trench; depositing a first insulator layer over the first conductor layer in the first trench; etching a second trench in the substrate at an angle to the first trench; depositing a second insulator layer in the second trench; depositing a second conductor layer over the second insulator layer in the second trench; and depositing phase change material. The deposited phase change material is in contact with the first conductor layer and the second conductor layer.
摘要翻译： 一种在衬底上制造相变存储单元的方法。 该方法包括：蚀刻衬底中的第一沟槽; 在第一沟槽中沉积第一导体层; 在所述第一沟槽中的所述第一导体层上沉积第一绝缘体层; 以与第一沟槽成一定角度蚀刻衬底中的第二沟槽; 在所述第二沟槽中沉积第二绝缘体层; 在所述第二沟槽中的所述第二绝缘体层上沉积第二导体层; 并沉积相变材料。 沉积的相变材料与第一导体层和第二导体层接触。
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公开(公告)号：US20120226963A1
公开(公告)日：2012-09-06
申请号：US13040531
申请日：2011-03-04
CPC分类号： G11C29/52 , G06F11/1048 , G11C11/5628 , G11C11/5642 , G11C13/00 , G11C16/00 , G11C29/42 , G11C29/76 , G11C2029/0409 , G11C2029/0411
摘要： Bad block management for flash memory including a method for storing data. The method includes receiving a write request that includes write data. A block of memory is identified for storing the write data. The block of memory includes a plurality of pages. A bit error rate (BER) of the block of memory is determined and expanded write data is created from the write data in response to the BER exceeding a BER threshold. The expanded write data is characterized by an expected BER that is lower than the BER threshold. The expanded write data is encoded using an error correction code (ECC). The encoded expanded write data is written to the block of memory.
摘要翻译： 用于闪存的坏块管理，包括用于存储数据的方法。 该方法包括接收包括写数据的写请求。 识别用于存储写入数据的存储器块。 存储器块包括多个页面。 确定存储器块的误码率（BER），并响应于超过BER阈值的BER从写入数据产生扩展写入数据。 扩展的写入数据的特征在于低于BER阈值的预期BER。 扩展的写入数据使用纠错码（ECC）进行编码。 编码的扩展写入数据被写入存储器块。
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35.发明申请公开(公告)号：US20120218814A1
公开(公告)日：2012-08-30
申请号：US13034936
申请日：2011-02-25
CPC分类号： G11C7/1012 , G06F2213/0038 , G11C13/0004 , G11C13/0069 , G11C2013/008
摘要： A memory system that includes a plurality of memory arrays having memory cells characterized by a variable write time. The memory system also includes a memory bus configured to receive write commands, and a plurality of data buffers configured to communicate with the memory arrays. The memory system further includes an address buffer configured to communicate with the memory arrays to store the write addresses. A mechanism configured to receive a write command and to split a data line received with the write command into a number of parts is also included in the memory system. The parts of the data line are stored in different data buffers and the writing of the parts of the data line to memory arrays at the write address is initiated. The write command is completed when write completion signals specifying the write address have been received from all of the memory arrays.
摘要翻译： 一种存储器系统，其包括具有由可变写入时间表征的存储器单元的多个存储器阵列。 存储器系统还包括被配置为接收写入命令的存储器总线以及被配置为与存储器阵列进行通信的多个数据缓冲器。 存储器系统还包括配置为与存储器阵列通信以存储写入地址的地址缓冲器。 被配置为接收写入命令并将用写入命令接收的数据线分割成多个部件的机构也包括在存储器系统中。 数据线的部分存储在不同的数据缓冲器中，并且开始将写入地址的数据线的部分写入存储器阵列。 当从所有存储器阵列接收到指定写入地址的写入完成信号时，写入命令完成。
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公开(公告)号：US20120127790A1
公开(公告)日：2012-05-24
申请号：US13355833
申请日：2012-01-23
申请人： Ibrahim M. Elfadel , Michele M. Franceschini , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
发明人： Ibrahim M. Elfadel , Michele M. Franceschini , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
CPC分类号： G11C8/10 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C27/005 , G11C2013/0083
摘要： Selecting bins in a memory by receiving a target cost for performing writes at an analog memory that is capable of storing a range of values. Possible bins that may be created in the range of values and a cost associated with each possible bin are determined. Each possible bin includes one or more of the values. A group of bins are identified, the group of bins are among the possible bins with associated costs that are within a threshold of the target cost. A maximum number of bins are selected from the group of bins that have non-overlapping values. The selected bins are stored along with the values of the selected bins utilized to encode and decode contents of the analog memory.
摘要翻译： 通过接收在能够存储一定范围的值的模拟存储器上执行写入的目标成本来选择存储器中的存储器。 确定可能在值范围内创建的可能的仓和与每个可能仓相关联的成本。 每个可能的仓包括一个或多个值。 识别出一组垃圾箱，这些垃圾箱是可能的垃圾箱，其相关成本在目标成本的阈值之内。 从具有非重叠值的分组组中选择最大数量的分区。 所选择的存储槽与用于对模拟存储器的内容进行编码和解码的所选择的存储器的值一起存储。
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公开(公告)号：US08125809B2
公开(公告)日：2012-02-28
申请号：US12566430
申请日：2009-09-24
申请人： Ibrahim M. Elfadel , Michele M. Franceschini , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
发明人： Ibrahim M. Elfadel , Michele M. Franceschini , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
IPC分类号： G11C27/00
CPC分类号： G11C8/10 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C27/005 , G11C2013/0083
摘要： An analog memory having adjustable write bins including a system for writing to the memory. The system includes a write apparatus interpreting one or more write control signals, generating a write signal, and applying the write signal at a selected memory location to store a desired content. The selected memory location is subject to data dependent noise and is capable of storing a range of values grouped into “n” bins configured such that the average cost to write to at least “n-1” of the bins is within a threshold of a target cost for the selected analog memory location. The system also includes a read apparatus. The system further includes write control circuitry that includes a write signal selector selecting the one or more write control signals responsive to the desired content, current content of the selected memory location, and a bin associated with the desired content.
摘要翻译： 具有可调节写入箱的模拟存储器，包括用于向存储器写入的系统。 该系统包括解释一个或多个写入控制信号的写入装置，产生写入信号，以及在选择的存储器位置处施加写入信号以存储所需的内容。 所选择的存储器位置受到数据相关噪声的影响，并且能够存储被分配到“n”个存储槽中的值的范围，其被配置为使得写入至少“n-1”个存储单元的平均成本在 所选模拟存储器位置的目标成本。 该系统还包括读取装置。 该系统还包括写控制电路，其包括响应于期望内容选择一个或多个写入控制信号的写入信号选择器，所选择的存储器位置的当前内容以及与期望内容相关联的存储区。
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公开(公告)号：US20110320881A1
公开(公告)日：2011-12-29
申请号：US12822508
申请日：2010-06-24
申请人： John S. Dodson , Frank D. Ferraiolo , Michele M. Franceschini , Kevin C. Gower , Lisa C. Gower , Ashish Jagmohan , Luis A. Lastras-Montano , Kenneth L. Wright
发明人： John S. Dodson , Frank D. Ferraiolo , Michele M. Franceschini , Kevin C. Gower , Lisa C. Gower , Ashish Jagmohan , Luis A. Lastras-Montano , Kenneth L. Wright
IPC分类号： G06F11/34
CPC分类号： G06F11/10 , G06F11/2005 , H04L1/0061 , H04L2001/0096
摘要： Isolation of faulty links in a transmission medium including a method that includes receiving an atomic data unit via a multi-link transmission medium that has a plurality of transmission links An error condition is detected and it is determined that the error condition is isolated to a single transmission link. It is determined if the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer. If the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer then: identifying the single transmission link as a faulty transmission link; resetting the timer; and outputting an identifier of the single transmission link.
摘要翻译： 隔离传输介质中的故障链路，包括包括通过具有多个传输链路的多链路传输介质接收原子数据单元的方法检测到错误状况，并且确定错误状况被隔离为单个 传输链路。 在由定时器指定的间隔内，确定单个传输链路是否已经被隔离为先前被隔离的传输链路指定的次数。 如果单个传输链路在由定时器指定的间隔内已经被隔离为失败的传输链路指定的次数，则：将单个传输链路识别为有故障的传输链路; 重置定时器; 并输出单个传输链路的标识符。
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公开(公告)号：US20110252215A1
公开(公告)日：2011-10-13
申请号：US12757738
申请日：2010-04-09
IPC分类号： G06F12/02
CPC分类号： G11C11/5628 , G06F12/0238 , G11C11/5678 , G11C13/0004 , G11C2211/5641 , Y02D10/13
摘要： A computer memory with dynamic cell density including a method that obtains a target size for a first memory region. The first memory region includes first memory units operating at a first density. The first memory units are includes in a memory in a memory system. The memory is operable at the first density and a second density. The method also includes: determining that a current size of the first memory region is not within a threshold of the target size and that the first memory region is smaller than the target size; identifying a second memory unit currently operating at the second density in a second memory region, the second memory unit included in the memory; and dynamically reassigning, during normal system operation, the second memory unit into the first memory region, the second memory unit operating at the first density after being reassigned to the first memory region.
摘要翻译： 一种具有动态单元密度的计算机存储器，包括获得第一存储器区域的目标尺寸的方法。 第一存储器区域包括以第一密度操作的第一存储器单元。 第一存储器单元包括在存储器系统的存储器中。 存储器可在第一密度和第二密度下操作。 所述方法还包括：确定所述第一存储器区域的当前大小不在所述目标大小的阈值内，并且所述第一存储器区域小于所述目标大小; 识别当前在第二存储器区域以第二密度操作的第二存储器单元，所述第二存储器单元包括在存储器中; 以及在正常系统操作期间将所述第二存储器单元动态地重新分配到所述第一存储器区域中，所述第二存储器单元在被重新分配给所述第一存储器区域之后以所述第一密度操作。
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40.发明授权公开(公告)号：US08023345B2
公开(公告)日：2011-09-20
申请号：US12391693
申请日：2009-02-24
申请人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
发明人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
CPC分类号： G11C29/02 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C29/021 , G11C29/028 , G11C2013/0092
摘要： Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.
摘要翻译： 提供了用于向内存位置迭代地写入内容的系统，方法和设备。 统计模型用于确定将所需内容写入存储器位置的脉冲序列。 内容可以表示为在存储单元中存储一个或多个位的范围内的电阻值。 对于相变存储器，基于期望的电阻范围来选择自适应复位脉冲和一个或多个退火脉冲。 读取存储器单元的电阻值可提供反馈以确定整体脉冲应用策略中的调整。 统计模型和查询表可用于选择和修改脉冲。 自适应地更新统计模型和查找表可以减少循环迭代的次数以将存储器单元的电阻值移动到期望的电阻范围。
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