公开(公告)号：US07332754B2

公开(公告)日：2008-02-19

申请号：US11022814

申请日：2004-12-28

申请人： Takashi Uno ,  Manabu Yanagihara ,  Hidetoshi Ishida ,  Tsuyoshi Tanaka

发明人： Takashi Uno ,  Manabu Yanagihara ,  Hidetoshi Ishida ,  Tsuyoshi Tanaka

IPC分类号： H01L29/80

CPC分类号： H01L27/1203 ,  H01L29/8126

摘要： In the semiconductor switch of the present invention, the gate electrode, source electrode and drain electrode are formed such that the distance between the gate and the drain of an MESFET, assuming a shunt FET, is longer than the distance between the gate and the drain of an MESFET, assuming a through FET, so that the gate breakdown voltage of the MESFET, assuming a shunt FET, is increased without changing the gate breakdown voltage of the MESFET, assuming a through FET.

摘要翻译： 在本发明的半导体开关中，栅电极，源电极和漏极形成为使得MESFET的栅极和漏极之间的距离（假设分流FET）比栅极和漏极之间的距离长 假定通过FET，MESFET的假定为通过FET的MESFET的栅极击穿电压在不改变MESFET的栅极击穿电压的情况下增加，并且假定为通过FET，所以增加了MESFET的栅极击穿电压。

公开(公告)号：US20070210332A1

公开(公告)日：2007-09-13

申请号：US11681408

申请日：2007-03-02

申请人： Hiroaki UENO ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Manabu Yanagihara ,  Yutaka Hirose ,  Masahiro Hikita

发明人： Hiroaki UENO ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Manabu Yanagihara ,  Yutaka Hirose ,  Masahiro Hikita

IPC分类号： H01L31/00

CPC分类号： H01L29/7786 ,  H01L29/2003

摘要： It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform. An insulating film 18 with a dielectric constant higher than that of the barrier layer is further inserted between a gate electrode 16 and the barrier layers 13, so that an improvement in gm and a reduction in gate leakage current can be achieved.

摘要翻译： 本发明的一个目的是提供一种半导体器件，其可以同时实现HFET的常闭模式和改进的最大值，并进一步实现gm的改善 和栅极漏电流的减小。 为了在栅电极正下方的基板11的操作层12上保持薄势垒层13，主要用于实现常关模式并且还实现高I max， 配置成使得栅极和源极区域之间以及栅极和漏极区域之间的半导体层17可以增加阻挡层13的厚度。 因此与阻挡层的厚度被设计为均匀的FET相比，可以实现常关模式和I 的改善。 介电常数高于阻挡层的绝缘膜18进一步插入在栅电极16和阻挡层13之间，从而改善gm和栅极漏电流的减小 可以实现。

公开(公告)号：US07148557B2

公开(公告)日：2006-12-12

申请号：US10650702

申请日：2003-08-29

申请人： Manabu Yanagihara ,  Naohiro Tsurumi ,  Tsuyoshi Tanaka ,  Daisuke Ueda

发明人： Manabu Yanagihara ,  Naohiro Tsurumi ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC分类号： H01L27/082

CPC分类号： H01L29/66318 ,  H01L29/0817 ,  H01L29/42304 ,  H01L29/7371

摘要： A bipolar transistor includes: a first semiconductor layer having an intrinsic base region and an extrinsic base region; and a second semiconductor layer having a portion located on the intrinsic base region to be an emitter region or a collector region. A capacitive film is provided on the extrinsic base region using the same semiconductor material as that for the second semiconductor layer. A base electrode is formed on the first semiconductor layer to cover the capacitive film and the extrinsic base region.

摘要翻译： 双极晶体管包括：具有本征基极区域和外部基极区域的第一半导体层; 以及第二半导体层，其具有位于本征基极区上的作为发射极区域或集电极区域的部分。 使用与第二半导体层相同的半导体材料在非本征基极区域上提供电容膜。 在第一半导体层上形成基极以覆盖电容膜和外部基极区。

公开(公告)号：US20060273347A1

公开(公告)日：2006-12-07

申请号：US11433734

申请日：2006-05-15

申请人： Masahiro Hikita ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

发明人： Masahiro Hikita ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

IPC分类号： H01L31/00

CPC分类号： H01L29/7786 ,  H01L29/0843 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/432 ,  H01L29/66462 ,  H01L29/7783

摘要： An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased.

摘要翻译： 依次形成AlN缓冲层，未掺杂的GaN层，未掺杂的AlGaN层，p型GaN层和重掺杂的p型GaN层。 栅电极与重掺杂的p型GaN层形成欧姆接触。 源电极和漏电极设置在未掺杂的AlGaN层上。 通过在未掺杂的AlGaN层和未掺杂的GaN层和p型GaN层之间的界面处产生的二维电子气在栅极区域中形成pn结，从而可以提高栅极电压。

公开(公告)号：US20060157729A1

公开(公告)日：2006-07-20

申请号：US11325340

申请日：2006-01-05

申请人： Hiroaki Ueno ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Manabu Yanagihara ,  Yutaka Hirose ,  Masahiro Hikita

发明人： Hiroaki Ueno ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Manabu Yanagihara ,  Yutaka Hirose ,  Masahiro Hikita

IPC分类号： H01L33/00

CPC分类号： H01L29/7786 ,  H01L29/2003

摘要： It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform. An insulating film 18 with a dielectric constant higher than that of the barrier layer is further inserted between a gate electrode 16 and the barrier layers 13, so that an improvement in gm and a reduction in gate leakage current can be achieved.

摘要翻译： 本发明的一个目的是提供一种半导体器件，其可以同时实现HFET的常闭模式和改进的最大值，并进一步实现gm的改善 和栅极漏电流的减小。 为了在栅电极正下方的基板11的操作层12上保持薄势垒层13，主要用于实现常关模式并且还实现高I max， 配置成使得栅极和源极区域之间以及栅极和漏极区域之间的半导体层17可以增加阻挡层13的厚度。 因此与阻挡层的厚度被设计为均匀的FET相比，可以实现常关模式和I 的改善。 介电常数高于阻挡层的绝缘膜18进一步插入在栅电极16和阻挡层13之间，从而改善gm和栅泄漏电流的降低 可以实现。

公开(公告)号：US20060060895A1

公开(公告)日：2006-03-23

申请号：US11193417

申请日：2005-08-01

申请人： Masahiro Hikita ,  Hiroaki Ueno ,  Yutaka Hirose ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

发明人： Masahiro Hikita ,  Hiroaki Ueno ,  Yutaka Hirose ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

IPC分类号： H01L31/112 ,  H01L29/20 ,  H01L29/80

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/4175

摘要： In the structure of a semiconductor device of the present invention, a first source electrode is connected to a conductive substrate through a via hole, and a second source electrode is formed. Thus, even if a high reverse voltage is applied between a gate electrode and a drain electrode, electric field concentration likely to occur at an edge of the gate electrode closer to the drain electrode can be effectively dispersed or relaxed. Moreover, the conductive substrate is used as a substrate for forming element formation layers, so that a via hole penetrating the substrate to reach the backside thereof does not have to be formed in the conductive substrate. Thus, with the strength necessary for the conductive substrate maintained, the first source electrode can be electrically connected to a backside electrode.

摘要翻译： 在本发明的半导体器件的结构中，第一源极通过通孔与导电性基板连接，形成第二源电极。 因此，即使在栅电极和漏极之间施加高的反向电压，也可以有效地分散或放松在栅电极的靠近漏电极的边缘处可能发生的电场集中。 此外，导电性基板用作形成元件形成层的基板，从而不必在导电性基板上形成贯穿基板到达其背面的通路孔。 因此，由于保持导电基板所需的强度，第一源电极可以电连接到背面电极。

公开(公告)号：US20050264341A1

公开(公告)日：2005-12-01

申请号：US11138474

申请日：2005-05-27

申请人： Masahiro Hikita ,  Manabu Yanagihara ,  Daisuke Ueda

发明人： Masahiro Hikita ,  Manabu Yanagihara ,  Daisuke Ueda

IPC分类号： H01P1/15 ,  H03K17/06 ,  H03K17/687 ,  H04B1/44

CPC分类号： H03K17/6871 ,  H03K17/063

摘要： The present invention, which aims at providing a semiconductor switch capable of reducing harmonic distortion, is made up of: an input terminal 101; an output terminal 102; a through FET 106 that is connected serially to the signal path between the input terminal 101 and the output terminal 102; a shunt FET 107 that is connected in between the output terminal 102 and the ground; and a distortion reducing circuit 120 that is connected in parallel with the through FET 106. In this semiconductor switch, the distortion reducing circuit 120 includes: a first diode 109 and a second diode 110 that are placed in parallel with each other; a first constant voltage source 111 and a second constant voltage source 112 that are placed in parallel with each other; and a FET 108.

摘要翻译： 旨在提供能够减少谐波失真的半导体开关的本发明由输入端子101构成， 输出端子102; 与输入端子101和输出端子102之间的信号路径串联连接的贯通FET106; 连接在输出端子102和地之间的并联FET107; 以及与通过FET 106并联连接的失真减小电路120。 在该半导体开关中，失真减少电路120包括：彼此平行放置的第一二极管109和第二二极管110; 彼此平行放置的第一恒定电压源111和第二恒定电压源112; 和FET 108。

公开(公告)号：US20050151208A1

公开(公告)日：2005-07-14

申请号：US11022814

申请日：2004-12-28

申请人： Takashi Uno ,  Manabu Yanagihara ,  Hidetoshi Ishida ,  Tsuyoshi Tanaka

发明人： Takashi Uno ,  Manabu Yanagihara ,  Hidetoshi Ishida ,  Tsuyoshi Tanaka

IPC分类号： H01L27/095 ,  H01L27/12 ,  H01L29/812 ,  H01L21/336 ,  H01L29/94

CPC分类号： H01L27/1203 ,  H01L29/8126

摘要： In the semiconductor switch of the present invention, the gate electrode, source electrode and drain electrode are formed such that the distance between the gate and the drain of an MESFET, assuming a shunt FET, is longer than the distance between the gate and the drain of an MESFET, assuming a through FET, so that the gate breakdown voltage of the MESFET, assuming a shunt FET, is increased without changing the gate breakdown voltage of the MESFET, assuming a through FET.

摘要翻译： 在本发明的半导体开关中，栅电极，源电极和漏极形成为使得MESFET的栅极和漏极之间的距离（假设分流FET）比栅极和漏极之间的距离长 假定通过FET，MESFET的假定为通过FET的MESFET的栅极击穿电压在不改变MESFET的栅极击穿电压的情况下增加，并且假定为通过FET，所以增加了MESFET的栅极击穿电压。

公开(公告)号：US06852580B2

公开(公告)日：2005-02-08

申请号：US10150326

申请日：2002-05-20

申请人： Manabu Yanagihara ,  Tsuyoshi Tanaka ,  Akihisa Sugimura

发明人： Manabu Yanagihara ,  Tsuyoshi Tanaka ,  Akihisa Sugimura

IPC分类号： H01L21/328 ,  G05F3/20 ,  H03F1/30 ,  H01L21/338

CPC分类号： H03F1/302 ,  G05F3/205

摘要： The invention provides a bias circuit for suppressing change with temperature of an idle current of a power transistor and a semiconductor device including the bias circuit. The bias circuit includes a first bipolar transistor having an emitter, a base and a collector, and at least one Schottky diode connected to the base of the first bipolar transistor, and the at least one Schottky diode is provided for supplying a base potential for suppressing a collector current of the first bipolar transistor from changing in accordance with temperature change.

摘要翻译： 本发明提供一种用于抑制功率晶体管的空载电流随温度变化的偏置电路和包括该偏置电路的半导体器件。 偏置电路包括具有发射极，基极和集电极的第一双极晶体管和连接到第一双极晶体管的基极的至少一个肖特基二极管，并且提供至少一个肖特基二极管以提供用于抑制的基极电位 第一双极晶体管的集电极电流根据温度变化而变化。

公开(公告)号：US08779438B2

公开(公告)日：2014-07-15

申请号：US13569014

申请日：2012-08-07

申请人： Masahiro Hikita ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

发明人： Masahiro Hikita ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

IPC分类号： H01L29/15 ,  H01L31/0256 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78

CPC分类号： H01L29/7786 ,  H01L29/0843 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/432 ,  H01L29/66462 ,  H01L29/7783

摘要： An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased.

摘要翻译： 依次形成AlN缓冲层，未掺杂的GaN层，未掺杂的AlGaN层，p型GaN层和重掺杂的p型GaN层。 栅电极与重掺杂的p型GaN层形成欧姆接触。 源电极和漏电极设置在未掺杂的AlGaN层上。 通过在未掺杂的AlGaN层和未掺杂的GaN层和p型GaN层之间的界面处产生的二维电子气在栅极区域中形成pn结，从而可以提高栅极电压。