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公开(公告)号：US06852580B2
公开(公告)日：2005-02-08
申请号：US10150326
申请日：2002-05-20
IPC分类号： H01L21/328 , G05F3/20 , H03F1/30 , H01L21/338
摘要： The invention provides a bias circuit for suppressing change with temperature of an idle current of a power transistor and a semiconductor device including the bias circuit. The bias circuit includes a first bipolar transistor having an emitter, a base and a collector, and at least one Schottky diode connected to the base of the first bipolar transistor, and the at least one Schottky diode is provided for supplying a base potential for suppressing a collector current of the first bipolar transistor from changing in accordance with temperature change.
摘要翻译： 本发明提供一种用于抑制功率晶体管的空载电流随温度变化的偏置电路和包括该偏置电路的半导体器件。 偏置电路包括具有发射极，基极和集电极的第一双极晶体管和连接到第一双极晶体管的基极的至少一个肖特基二极管，并且提供至少一个肖特基二极管以提供用于抑制的基极电位 第一双极晶体管的集电极电流根据温度变化而变化。
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公开(公告)号：US06407617B1
公开(公告)日：2002-06-18
申请号：US09714131
申请日：2000-11-17
IPC分类号： H03K301
摘要： The invention provides a bias circuit for suppressing change with temperature of an idle current of a power transistor and a semiconductor device including the bias circuit. The bias circuit includes a first bipolar transistor having an emitter, a base and a collector, and at least one Schottky diode connected to the base of the first bipolar transistor, and the at least one Schottky diode is provided for supplying a base potential for suppressing a collector current of the first bipolar transistor from changing in accordance with temperature change.
摘要翻译： 本发明提供一种用于抑制功率晶体管的空载电流随温度变化的偏置电路和包括该偏置电路的半导体器件。 偏置电路包括具有发射极，基极和集电极的第一双极晶体管和连接到第一双极晶体管的基极的至少一个肖特基二极管，并且提供至少一个肖特基二极管以提供用于抑制的基极电位 第一双极晶体管的集电极电流根据温度变化而变化。
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公开(公告)号：US07898002B2
公开(公告)日：2011-03-01
申请号：US11890480
申请日：2007-08-07
IPC分类号： H01L21/337 , H01L21/335
CPC分类号： H01L29/7786 , H01L29/1066 , H01L29/2003 , H01L29/4175 , H01L29/432 , H01L29/66462
摘要： A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer formed over the substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a larger band gap energy than the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer and including a p-type nitride semiconductor with at least a single-layer structure; a gate electrode formed on the third nitride semiconductor layer; and a source electrode and a drain electrode formed in regions located on both sides of the gate electrode, respectively. The third nitride semiconductor layer has a thickness greater in a portion below the gate electrode than in a portion below the side of the gate electrode.
摘要翻译： 氮化物半导体器件包括：衬底; 形成在所述基板上的第一氮化物半导体层; 形成在所述第一氮化物半导体层上并且具有比所述第一氮化物半导体层更大的带隙能量的第二氮化物半导体层; 形成在所述第二氮化物半导体层上并且包括具有至少单层结构的p型氮化物半导体的第三氮化物半导体层; 形成在所述第三氮化物半导体层上的栅极; 以及分别形成在位于栅电极两侧的区域中的源电极和漏电极。 所述第三氮化物半导体层的厚度比所述栅极电极侧的部分的厚度大。
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公开(公告)号：US20100327293A1
公开(公告)日：2010-12-30
申请号：US12880704
申请日：2010-09-13
IPC分类号： H01L29/20
CPC分类号： H01L29/7786 , H01L29/0843 , H01L29/1066 , H01L29/2003 , H01L29/432 , H01L29/66462 , H01L29/7783
摘要： An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased.
摘要翻译： 依次形成AlN缓冲层，未掺杂的GaN层，未掺杂的AlGaN层，p型GaN层和重掺杂的p型GaN层。 栅电极与重掺杂的p型GaN层形成欧姆接触。 源电极和漏电极设置在未掺杂的AlGaN层上。 通过在未掺杂的AlGaN层和未掺杂的GaN层和p型GaN层之间的界面处产生的二维电子气在栅极区域中形成pn结，从而可以提高栅极电压。
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公开(公告)号：US20100244045A1
公开(公告)日：2010-09-30
申请号：US12795143
申请日：2010-06-07
IPC分类号： H01L29/20
CPC分类号： H01L29/66462 , H01L29/2003 , H01L29/205 , H01L29/402 , H01L29/7787 , H01L29/872
摘要： A semiconductor device includes a first semiconductor layer which is formed above a substrate, a Schottky electrode and an ohmic electrode which are formed on the first semiconductor layer to be spaced from each other and a second semiconductor layer which is formed to cover the first semiconductor layer with the Schottky electrode and the ohmic electrode exposed. The second semiconductor layer has a larger band gap than that of the first semiconductor layer.
摘要翻译： 半导体器件包括形成在衬底上的第一半导体层，形成在第一半导体层上彼此间隔开的肖特基电极和欧姆电极以及形成为覆盖第一半导体层的第二半导体层 肖特基电极和欧姆电极暴露。 第二半导体层具有比第一半导体层更大的带隙。
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公开(公告)号：US07612426B2
公开(公告)日：2009-11-03
申请号：US11272878
申请日：2005-11-15
IPC分类号： H01L29/872
CPC分类号： H01L29/872 , H01L21/26506 , H01L27/0605 , H01L27/0814 , H01L29/0692 , H01L29/417 , H01L29/66143
摘要： A Schottky barrier diode includes a first semiconductor layer and a second semiconductor layer successively formed above a semiconductor substrate with a buffer layer formed between the first and second semiconductor layers and the semiconductor substrate. A Schottky electrode and an ohmic electrode spaced from each other are formed on the second semiconductor layer, and a back face electrode is formed on the back face of the semiconductor substrate. The Schottky electrode or the ohmic electrode is electrically connected to the back face electrode through a via penetrating through at least the buffer layer.
摘要翻译： 肖特基势垒二极管包括在半导体衬底上连续形成的第一半导体层和形成在第一和第二半导体层与半导体衬底之间的缓冲层的第二半导体层。 在第二半导体层上形成有彼此间隔开的肖特基电极和欧姆电极，在半导体基板的背面形成背面电极。 肖特基电极或欧姆电极通过贯穿至少缓冲层的通孔电连接到背面电极。
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公开(公告)号：US07605441B2
公开(公告)日：2009-10-20
申请号：US11730422
申请日：2007-04-02
IPC分类号： H01L27/095 , H01L21/28 , H01L29/47
CPC分类号： H01L29/872 , H01L29/2003 , H01L29/66212
摘要： A semiconductor device includes: a semiconductor layer made of a group-III nitride semiconductor and having a first surface and a second surface opposed to the first surface; a Schottky electrode formed on the first surface of the semiconductor layer; and an ohmic electrode electrically connected to the second surface of the semiconductor layer. The semiconductor layer has, in at least the upper portion thereof, highly-resistive regions selectively formed to have a high resistance.
摘要翻译： 半导体器件包括：由III族氮化物半导体制成并具有与第一表面相对的第一表面和第二表面的半导体层; 形成在半导体层的第一表面上的肖特基电极; 以及与半导体层的第二表面电连接的欧姆电极。 半导体层至少在其上部具有选择性地形成为具有高电阻的高电阻区域。
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公开(公告)号：US20090121775A1
公开(公告)日：2009-05-14
申请号：US11995040
申请日：2006-06-27
申请人： Daisuke Ueda , Tsuyoshi Tanaka , Yasuhiro Uemoto , Tetsuzo Ueda , Manabu Yanagihara , Masahiro Hikita , Hiroaki Ueno
发明人： Daisuke Ueda , Tsuyoshi Tanaka , Yasuhiro Uemoto , Tetsuzo Ueda , Manabu Yanagihara , Masahiro Hikita , Hiroaki Ueno
IPC分类号： H01L29/207 , H03K17/687
CPC分类号： H01L29/739 , H01L29/1066 , H01L29/2003 , H01L29/4175 , H01L29/7786
摘要： In a transistor, an AlN buffer layer 102, an undoped GaN layer 103, an undoped AlGaN layer 104, a p-type control layer 105, and a p-type contact layer 106 are formed in this order on a sapphire substrate 101. The transistor further includes a gate electrode 110 in ohmic contact with the p-type contact layer 106, and a source electrode 108 and a drain electrode 109 provided on the undoped AlGaN layer 104. By applying a positive voltage to the p-type control layer 105, holes are injected into a channel to increase a current flowing in the channel.
摘要翻译： 在晶体管中，在蓝宝石衬底101上依次形成AlN缓冲层102，未掺杂的GaN层103，未掺杂的AlGaN层104，p型控制层105和p型接触层106。 晶体管还包括与p型接触层106欧姆接触的栅电极110以及设置在未掺杂的AlGaN层104上的源电极108和漏极109.通过向p型控制层105施加正电压 ，孔被注入到通道中以增加在通道中流动的电流。
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公开(公告)号：US20070126115A1
公开(公告)日：2007-06-07
申请号：US11593617
申请日：2006-11-07
IPC分类号： H01L23/34
CPC分类号： H05K3/28 , H01L21/563 , H01L23/3732 , H01L24/45 , H01L24/48 , H01L2224/13144 , H01L2224/16 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/83951 , H01L2224/8592 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01079 , H01L2924/1306 , H01L2924/13091 , H01L2924/15153 , H01L2924/1517 , H05K1/0209 , H05K2201/0179 , H05K2201/0323 , H05K2201/09045 , H01L2924/00 , H01L2224/85399 , H01L2224/05599
摘要： A package substrate has a substrate body on which an electronic component is mounted. The substrate body is formed at its top or back surface with a diamond film, a diamond-like carbon film or a carbon film.
摘要翻译： 封装基板具有安装电子部件的基板主体。 基板主体在其顶部或背面形成有金刚石膜，类金刚石碳膜或碳膜。
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公开(公告)号：US07217960B2
公开(公告)日：2007-05-15
申请号：US11325340
申请日：2006-01-05
申请人： Hiroaki Ueno , Tetsuzo Ueda , Yasuhiro Uemoto , Daisuke Ueda , Tsuyoshi Tanaka , Manabu Yanagihara , Yutaka Hirose , Masahiro Hikita
发明人： Hiroaki Ueno , Tetsuzo Ueda , Yasuhiro Uemoto , Daisuke Ueda , Tsuyoshi Tanaka , Manabu Yanagihara , Yutaka Hirose , Masahiro Hikita
IPC分类号： H01L33/00
CPC分类号： H01L29/7786 , H01L29/2003
摘要： It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform. An insulating film 18 with a dielectric constant higher than that of the barrier layer is further inserted between a gate electrode 16 and the barrier layers 13, so that an improvement in gm and a reduction in gate leakage current can be achieved.
摘要翻译： 本发明的一个目的是提供一种半导体器件，其可以同时实现HFET的常闭模式和改进的最大值，并进一步实现gm的改善 和栅极漏电流的减小。 为了在栅电极正下方的基板11的操作层12上保持薄势垒层13，主要用于实现常关模式并且还实现高I max， 配置成使得栅极和源极区域之间以及栅极和漏极区域之间的半导体层17可以增加阻挡层13的厚度。 因此与阻挡层的厚度被设计为均匀的FET相比，可以实现常关模式和I 的改善。 介电常数高于阻挡层的绝缘膜18进一步插入在栅电极16和阻挡层13之间，从而改善gm和栅极漏电流的减小 可以实现。
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