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公开(公告)号：US20100164542A1
公开(公告)日：2010-07-01
申请号：US12722317
申请日：2010-03-11
申请人： Yasuhiro AGATA , Toshiaki Kawasaki , Masanori Shirahama , Ryuji Nishihara , Shinichi Sumi , Yasue Yamamoto , Hirohito Kikukawa
发明人： Yasuhiro AGATA , Toshiaki Kawasaki , Masanori Shirahama , Ryuji Nishihara , Shinichi Sumi , Yasue Yamamoto , Hirohito Kikukawa
IPC分类号： H03K19/173
CPC分类号： G11C5/063 , G11C5/14 , G11C17/165 , G11C17/18 , H01L2924/0002 , H01L2924/00
摘要： A system LSI includes an input/output section and a logic circuit section. The input/output section includes an I/O power source cell having a supply voltage higher than a power source for the logic circuit section and a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell. The logic circuit section includes an I/O power consuming circuit which uses the I/O power source cell as a power source. The I/O power consuming circuit is connected to a line leading from an I/O power source line in at least one of the plurality of I/O cells.
摘要翻译： 系统LSI包括输入/输出部分和逻辑电路部分。 输入/输出部分包括具有高于用于逻辑电路部分的电源的电源电压的I / O电源单元和设置有I / O电源线的多个I / O单元，用于提供 来自I / O电源单元的源电源。 逻辑电路部分包括使用I / O电源单元作为电源的I / O功耗电路。 I / O消耗电路连接到从多个I / O单元中的至少一个中的I / O电源线引出的线。
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公开(公告)号：US07602231B2
公开(公告)日：2009-10-13
申请号：US11526060
申请日：2006-09-25
CPC分类号： H02M3/07
摘要： A circuit includes a plurality of stages each including a MOS transistor and a capacitor of which one end is connected to one of a drain and a source of the MOS transistor. The plurality of stages are connected with each other by cascade connection of the MOS transistors. A gate of the MOS transistor is connected electrically to one of the drain and the source thereof in each stage, and a substrate for at least one pair of adjacent MOS transistors are connected electrically to one of the drain and the source of one of the pair. The back bias effect is suppressed, and the layout area is reduced. Further, a plurality of booster capacitors connected in series are provided in succeeding stages, thereby suppressing degradation of breakdown voltage of each capacitor.
摘要翻译： 电路包括多个级，每个级包括MOS晶体管和电容器，其一端连接到MOS晶体管的漏极和源极之一。 多个级通过MOS晶体管的级联连接而相互连接。 MOS晶体管的栅极在每个级中电连接到漏极和源极之一，并且用于至少一对相邻MOS晶体管的衬底电连接到该对之一的漏极和源极之一 。 背偏置效果被抑制，布局面积减小。 此外，在后续阶段提供串联连接的多个升压电容器，从而抑制每个电容器的击穿电压的劣化。
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公开(公告)号：US20090189226A1
公开(公告)日：2009-07-30
申请号：US12247647
申请日：2008-10-08
IPC分类号： H01L29/00
摘要： An electrical fuse circuit includes, in addition to an independent power supply switch circuit, a plurality of fuse bit cells, each including a fuse element one end of which is connected to an output of the power supply switch circuit, and a first MOS transistor connected to the other end of the fuse element, wherein a diode is connected between the ground potential and the power supply switch circuit as an ESD countermeasure. The gate oxide film thickness of transistors of the fuse bit cells is equal to that of a low-voltage logic-type transistor, not that of a high-voltage I/O-type transistor.
摘要翻译： 除了独立的电源开关电路之外，电熔丝电路还包括多个熔丝位单元，每个熔丝位单元包括一个熔丝元件，其一端连接到电源开关电路的输出端，第一MOS晶体管连接 连接到熔丝元件的另一端，其中二极管作为ESD对策连接在地电位和电源开关电路之间。 熔丝位单元的晶体管的栅极氧化膜厚度等于低压逻辑型晶体管的栅极氧化膜厚度，而不是高电压I / O型晶体管的晶体管的栅极氧化膜厚度。
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公开(公告)号：US20080186789A1
公开(公告)日：2008-08-07
申请号：US12021317
申请日：2008-01-29
IPC分类号： G11C17/16
CPC分类号： G11C17/18
摘要： A first transistor is connected in series with one end of a fuse element. A second transistor is connected in series with the other end of the fuse element. A current flows through the fuse element when both the first and second transistors are turned on.
摘要翻译： 第一晶体管与保险丝元件的一端串联连接。 第二晶体管与保险丝元件的另一端串联连接。 当第一和第二晶体管都导通时，电流流过熔丝元件。
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公开(公告)号：US20060158920A1
公开(公告)日：2006-07-20
申请号：US11324243
申请日：2006-01-04
IPC分类号： G11C17/00
CPC分类号： G11C17/18
摘要： An electrical fuse circuit of the present invention includes a plurality of electrical fuse cores (1) each of which has an electrical fuse element (3) and a switch transistor (4) connected in series with each other, and shift registers (2) connected to the plurality of electrical fuse cores (1) to program the electrical fuse elements (3). Program enable signals (Si) are sequentially generated and transferred by the shift registers (2), the switch transistors (4) are sequentially brought into conduct according to the program enable signals (Si) and the information of program data (Di), and the electrical fuse elements (3) are blown one by one.
摘要翻译： 本发明的电熔丝电路包括多个电熔丝芯（1），每个电熔丝芯具有彼此串联连接的电熔丝元件（3）和开关晶体管（4），并且移位寄存器（2）连接 到多个电熔丝芯（1）以编程电熔丝元件（3）。 程序使能信号（Si）由移位寄存器（2）依次产生和传送，开关晶体管（4）根据程序使能信号（Si）和程序数据（Di）的信息依次导通， 电熔丝元件（3）被一个接一个地吹出。
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公开(公告)号：US20050162954A1
公开(公告)日：2005-07-28
申请号：US11038025
申请日：2005-01-21
IPC分类号： G11C7/02 , G11C11/409 , G11C11/419 , G11C29/00 , G11C29/50 , H01L27/105
CPC分类号： G11C29/50 , G11C2029/1204 , G11C2029/5004
摘要： In a normal operation, an output of a differential amplifier for amplifying a difference between first and second bit cells is output as readout data. In a test mode, when a first control signal is set to be “H”, the output of the differential amplifier is fixed to be “H” and thus an output of the first bit cell is read out through gates.
摘要翻译： 在正常操作中，输出用于放大第一和第二位单元之间的差分的差分放大器的输出作为读出数据。 在测试模式中，当第一控制信号被设置为“H”时，差分放大器的输出被固定为“H”，从而通过门读出第一位单元的输出。
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公开(公告)号：US20050047236A1
公开(公告)日：2005-03-03
申请号：US10928366
申请日：2004-08-30
CPC分类号： G11C7/1096 , G11C7/062 , G11C7/1078
摘要： A semiconductor integrated circuit device includes: first and second nonvolatile memory elements; a first amplifier for amplifying an output signal from the first nonvolatile memory element to output the amplified signal; and a second amplifier for outputting to the first amplifier a control signal generated by amplifying an output signal from the second nonvolatile memory element. The second amplifier fixes the output signal from the first amplifier at a high potential or a low potential based on data stored in the second nonvolatile memory element.
摘要翻译： 一种半导体集成电路器件，包括：第一和第二非易失性存储元件; 第一放大器，用于放大来自第一非易失性存储器元件的输出信号以输出放大的信号; 以及第二放大器，用于向第一放大器输出通过放大来自第二非易失性存储元件的输出信号而产生的控制信号。 第二放大器基于存储在第二非易失性存储器元件中的数据，将来自第一放大器的输出信号固定在高电位或低电位。
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公开(公告)号：US06788565B2
公开(公告)日：2004-09-07
申请号：US10394262
申请日：2003-03-24
申请人： Masashi Agata , Kazunari Takahashi , Masanori Shirahama , Naoki Kuroda , Hiroyuki Sadakata , Ryuji Nishihara
发明人： Masashi Agata , Kazunari Takahashi , Masanori Shirahama , Naoki Kuroda , Hiroyuki Sadakata , Ryuji Nishihara
IPC分类号： G11C1140
CPC分类号： G11C11/405 , H01L27/108
摘要： A semiconductor memory device has a plurality of memory cells each having a first transistor, a second transistor having a source or drain connected to one portion of the source or drain of the first transistor, and a third transistor having a source or drain connected to the other portion of the source or drain of the first transistor. The first transistor accumulates, in the channel thereof, charges transferred from the second and third transistors.
摘要翻译： 半导体存储器件具有多个存储单元，每个存储单元具有第一晶体管，第二晶体管具有连接到第一晶体管的源极或漏极的一部分的源极或漏极;以及第三晶体管，源极或漏极连接到第一晶体管， 第一晶体管的源极或漏极的另一部分。 第一晶体管在其通道中累积从第二和第三晶体管传送的电荷。
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公开(公告)号：US20120169402A1
公开(公告)日：2012-07-05
申请号：US13417548
申请日：2012-03-12
IPC分类号： H01H37/76
CPC分类号： H01L27/0207 , G11C17/18 , H01L23/5256 , H01L27/0288 , H01L27/10 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes an electric fuse circuit and a program protective circuit. The electric fuse circuit includes a fuse element and a transistor connected together in series and placed between a program power supply and a grounding, and controlling sections. The program protective circuit is placed in parallel with the electric fuse circuit and between the program power supply and the grounding. When a surge voltage is applied between the program power supply and the grounding, the foregoing structure allows a part of a surge electric current can flow through the program protective circuit.
摘要翻译： 半导体器件包括电熔丝电路和程序保护电路。 电熔丝电路包括串联连接在一起的一个熔丝元件和一个晶体管，并放置在一个程序电源和一个接地之间，以及控制部分。 程序保护电路与电熔丝电路并联在程序电源和接地之间。 当在程序电源和接地之间施加浪涌电压时，上述结构允许一部分浪涌电流可以流过程序保护电路。
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公开(公告)号：US08094498B2
公开(公告)日：2012-01-10
申请号：US12792295
申请日：2010-06-02
IPC分类号： G11C16/04
CPC分类号： G11C16/0441 , G11C16/10 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： In a nonvolatile semiconductor memory device storing data by accumulating charges in a floating gate, memory units, each of which includes a first MOS transistor as a read device, a bit cell composed of a first capacitor as a capacitance coupling device and a second capacitor as an erase device, and a decode device including a second MOS transistor and a third MOS transistor, are arranged in array. This attains nonvolatile memory capable of bit by bit selective erase arranged in array to thus reduce the core area remarkably.
摘要翻译： 在通过在浮动栅极中积累电荷来存储数据的非易失性半导体存储器件中，每个包括作为读取器件的第一MOS晶体管的存储器单元，由作为电容耦合器件的第一电容器构成的位单元和第二电容器 擦除装置，以及包括第二MOS晶体管和第三MOS晶体管的解码装置。 这实现了能够排列成阵列的逐位选择性擦除的非易失性存储器，从而显着地减小了核心区域。
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