Method for adjusting a blood analyte measurement
    36.
    发明授权
    Method for adjusting a blood analyte measurement 失效
    用于调节血液分析物测量的方法

    公开(公告)号:US06825044B2

    公开(公告)日:2004-11-30

    申请号:US10301927

    申请日:2002-11-21

    IPC分类号: G01N2164

    摘要: A device and method for determining analyte concentrations within a material sample are provided. A modulating temperature gradient is induced in the sample and resultant, emitted infrared radiation is measured at selected analyte absorbance peaks and reference wavelengths. The modulating temperature gradient is controlled by a surface temperature modulation. A transfer function relating the surface temperature modulation to a modulation of the measured infrared radiation is provided. Phase and magnitude differences in the transfer function are detected. These phase and magnitude differences, having a relationship to analyte concentration, are measured, correlated and processed to determine analyte concentration in the material sample. A method for adjusting an analyte measurement is provided. The method provides a hydration correction process for calibration and correction whereby analyte concentrations within the material sample may be determined. The hydration correction process is particularly suitable for determining blood analyte concentrations within human tissue.

    摘要翻译: 提供了用于确定材料样品中的分析物浓度的装置和方法。 在样品中诱导调制温度梯度,并在所选分析物的吸收峰和参考波长处测量发射的红外辐射。 调制温度梯度由表面温度调制控制。 提供了将表面温度调制与测量的红外辐射的调制相关联的传递函数。 检测传递函数的相位和幅度差异。 测量,相关和处理与分析物浓度有关的这些相位和幅度差异,以确定材料样品中的分析物浓度。 提供了一种用于调节分析物测量的方法。 该方法提供用于校准和校正的水合校正过程,从而可以确定材料样品中的分析物浓度。 水合校正过程特别适用于测定人体组织内的血液分析物浓度。

    Circuit and method for computing a fast fourier transform
    37.
    发明授权
    Circuit and method for computing a fast fourier transform 有权
    用于计算快速傅里叶变换的电路和方法

    公开(公告)号:US06615227B2

    公开(公告)日:2003-09-02

    申请号:US10247144

    申请日:2002-09-19

    IPC分类号: G06F1714

    CPC分类号: G06F17/142

    摘要: A processing circuit is disclosed for computing a fast Fourier transform (FFT). In one embodiment, the processing circuit includes a memory device, a multiplier, a detector, a state machine, and a circuit for performing the 2's compliment of a coefficient. The memory storage device stores data values and coefficient (or twiddle) values. The detector integrates a data pointer with the state machine. The detector is designed to identify the symmetry lines (by memory address). The state machine, when notified by the detector that a line of symmetry has been encountered, appropriately adjusts either the coefficients, the imaginary sign, or the real sign for input to a multiplier.

    摘要翻译: 公开了一种用于计算快速傅里叶变换(FFT)的处理电路。 在一个实施例中,处理电路包括一个存储器件,一个乘法器,一个检测器,一个状态机以及一个用于执行2的系数的补偿的电路。 存储器存储设备存储数据值和系数(或旋转)值。 检测器将数据指针与状态机集成。 检测器设计用于识别对称线(通过存储器地址)。 状态机当被检测器通知已经遇到对称线时,适当地调整系数,虚拟符号或输入到乘法器的真实符号。

    Circuit for computing a fast fourier transform
    40.
    发明授权
    Circuit for computing a fast fourier transform 有权
    用于计算快速傅里叶变换的电路

    公开(公告)号:US06549925B1

    公开(公告)日:2003-04-15

    申请号:US09311969

    申请日:1999-05-14

    IPC分类号: G06F1500

    CPC分类号: G06F17/142

    摘要: The present invention is generally directed to a processing circuit for computing a fast Fourier transform (FFT). The present invention reflects the recognition that excessive reads to and writes from memory consume excessive amounts of power. Accordingly, the circuit of the present is specifically designed to minimize the number of reads and writes to memory. In addition, the circuit is designed so that processing parallelism may be achieved in order to reduce the total number of clock cycles required to compute a FFT. In accordance with one aspect of the invention, the processing circuit includes a data memory for storing data values, and a separate coefficient memory for storing coefficient (or twiddle) values. The circuit further includes a multiplier configured to multiply values received from the coefficient memory and another value retrieved from some other location. The circuit further includes a first adder configured to add a value output from the multiplier with a value retrieved from another location. The circuit further includes a second adder configured to add a value retrieved from the data memory with a value retrieved from another location. Finally, the circuit includes write-back data path disposed between the second adder and the data memory. The write-back data path is configured to write data output from the second adder to the data memory, to a location where a data value was previously retrieved.

    摘要翻译: 本发明一般涉及用于计算快速傅里叶变换(FFT)的处理电路。 本发明反映了对存储器的过度读取和写入消耗过多功率的认识。 因此,本发明的电路被专门设计成最小化对存储器的读取和写入的数量。 此外,电路被设计成使得可以实现处理并行性,以便减少计算FFT所需的时钟周期的总数。 根据本发明的一个方面,处理电路包括用于存储数据值的数据存储器和用于存储系数(或旋转)值的单独系数存储器。 电路还包括乘法器,其被配置为乘以从系数存储器接收的值和从某个其他位置检索的另一值。 电路还包括第一加法器,其被配置为将从乘法器输出的值与从另一位置检索的值相加。 电路还包括第二加法器,其被配置为将从数据存储器检索的值与从另一位置检索的值相加。 最后,电路包括设置在第二加法器和数据存储器之间的回写数据路径。 写回数据路径被配置为将从第二加法器输出的数据写入到数据存储器,到先前检索到数据值的位置。