公开(公告)号：US08504751B2

公开(公告)日：2013-08-06

申请号：US12960713

申请日：2010-12-06

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F13/24

CPC classification number: G06F13/24 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A package includes a first die and a second die. The dies are connected to each other through an interface. The package includes interrupt processing for detecting interrupt information and providing a packet in response to the interrupt information detection. The packet includes an address to which data in the packet is to be written. The interface is configured to transport the packet between the dies. A data store is provided to which the data is writable. An interrupt event is determined from data received in several packets.

Abstract translation: 包装包括第一模具和第二模具。 模具通过接口彼此连接。 该包装包括用于检测中断信息的中断处理和响应于中断信息检测提供分组。 分组包括要写入分组中的数据的地址。 该接口被配置为在信元之间传送数据包。 提供数据可写入的数据存储。 从几个数据包中接收的数据确定中断事件。

公开(公告)号：US08468381B2

公开(公告)日：2013-06-18

申请号：US12959005

申请日：2010-12-02

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F1/04 ,  G06F12/00 ,  G06F15/00 ,  G06F11/00 ,  H04L7/00

CPC classification number: H04L49/109 ,  G06F15/7825 ,  H01L2224/16225 ,  H01L2924/15311 ,  H04L49/101 ,  Y02D10/12 ,  Y02D10/13

Abstract: A package includes a first die and a second die. The dies are connected to each other through an interface. The interface is configured to transport both control signals and memory transactions. A synchronizer is provided on at least one of said first and second of said dies. The synchronizer is configured to cause any untransmitted control signal values to be transmitted across the interface.

Abstract translation: 包装包括第一模具和第二模具。 模具通过接口彼此连接。 接口配置为传输控制信号和存储器事务。 在所述第一和第二模具中的至少一个上提供同步器。 同步器被配置为使得任何未发送的控制信号值跨接口传输。

公开(公告)号：US20130031313A1

公开(公告)日：2013-01-31

申请号：US13560559

申请日：2012-07-27

Applicant: Stuart Ryan ,  Andrew Michael Jones

Inventor： Stuart Ryan ,  Andrew Michael Jones

IPC: G06F12/08

CPC classification number: G06F12/0897 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/0862 ,  G06F2212/6022

Abstract: A first cache arrangement including an input configured to receive a memory request from a second cache arrangement; a first cache memory for storing data; an output configured to provide a response to the memory request for the second cache arrangement; and a first cache controller; the first cache controller configured such that for the response to the memory request output by the output, the cache memory includes no allocation for data associated with the memory request.

Abstract translation: 一种第一高速缓存装置，包括被配置为从第二高速缓存装置接收存储器请求的输入; 用于存储数据的第一高速缓冲存储器; 输出，被配置为提供对所述第二高速缓存装置的所述存储器请求的响应; 和第一缓存控制器; 第一缓存控制器被配置为使得对于由输出输出的存储器请求的响应，高速缓存存储器不包括与存储器请求相关联的数据的分配。

公开(公告)号：US08260994B2

公开(公告)日：2012-09-04

申请号：US11415265

申请日：2006-05-01

Applicant: Stuart Ryan ,  Andrew Jones

Inventor： Stuart Ryan ,  Andrew Jones

IPC: G06F13/24 ,  G06F13/36

CPC classification number: G06F13/385 ,  G06F13/24 ,  G06F2213/0038

Abstract: An interface is described which has at least one chip side port with a first plurality of pins for conveying fields of a packet and first and second circuit side ports each port having a set of pins with a lower number than the first set of pins in the chip side port. The interface is constructed so that interrupt signals from an off-chip circuit can be conveyed on-chip in a manner such that the interrupt signals are indistinguishable from interrupt signals received from on-chip modules connected to an on-chip communication path. The same principle is applicable to power-down signals.

Abstract translation: 描述了具有至少一个芯片侧端口的接口，该芯片侧端口具有用于传送分组的场的第一多个引脚，以及第一和第二电路侧端口，每个端口具有一组具有比第一组引脚小的引脚的引脚 芯片侧端口。 该接口被构造成使得来自片外电路的中断信号可以以片上的方式传送，使得中断信号与从连接到片上通信路径的片上模块接收到的中断信号无法区分。 同样的原理适用于掉电信号。

公开(公告)号：US20120210093A1

公开(公告)日：2012-08-16

申请号：US13028383

申请日：2011-02-16

Applicant: Ignazio Antonino URZI ,  Philippe D'AUDIGIER ,  Olivier SAUVAGE ,  Stuart RYAN ,  Andrew Michael JONES

Inventor： Ignazio Antonino URZI ,  Philippe D'AUDIGIER ,  Olivier SAUVAGE ,  Stuart RYAN ,  Andrew Michael JONES

IPC: G06F12/02

CPC classification number: G06F13/385 ,  A01C7/04 ,  A01C7/20 ,  G06F15/173 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/014

Abstract: A package includes a die and at least one further die. The die has an interface configured to receive a transaction request from the further die via an interconnect and to transmit a response to the transaction request to said further die via the interconnect. The die also has mapping circuitry which is configured to receive the transaction request including at least first source identity information, wherein the first source identity information is associated with a source of the transaction request on the further die. The mapping circuitry is configured to modify the transaction request to replace the first source identity information with local source identity information, wherein that local source identity information is associated with the mapping circuitry. The mapping circuitry is configured to modify the received transaction request to provide said first source identity information in a further field.

Abstract translation: 包装包括模具和至少一个另外的模具。 管芯具有被配置为经由互连从另外的管芯接收事务请求并且经由互连将对事务请求的响应发送到所述另外管芯的接口。 芯片还具有映射电路，其被配置为接收包括至少第一源标识信息的事务请求，其中第一源标识信息与另外裸片上的事务请求的源相关联。 映射电路被配置为修改事务请求以用本地源标识信息替换第一源标识信息，其中本地源标识信息与映射电路相关联。 映射电路被配置为修改所接收的事务请求以在另外的字段中提供所述第一源标识信息。

公开(公告)号：US20110134705A1

公开(公告)日：2011-06-09

申请号：US12958622

申请日：2010-12-02

Applicant: Andrew Michael Jones ,  Stuart Ryan ,  Alberto Scandurra

Inventor： Andrew Michael Jones ,  Stuart Ryan ,  Alberto Scandurra

IPC: G11C7/00

CPC classification number: G11C7/10 ,  G06F13/16 ,  H01L23/5383 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2924/15311 ,  H04N21/426 ,  Y02D10/14

Abstract: A package includes a first die and a second die, at least one of said first and second dies being a memory. The dies are connected to each other through an interface. The interface is configured to transport both control signals and memory transactions. A multiplexer is provided to multiplex the control signals and memory transactions onto the interface such that a plurality of connections of said interface are shared by the control signals and the memory transactions.

Abstract translation: 包装包括第一管芯和第二管芯，所述第一和第二管芯中的至少一个是存储器。 模具通过接口彼此连接。 接口配置为传输控制信号和存储器事务。 提供多路复用器以将控制信号和存储器事务多路复用到接口上，使得所述接口的多个连接由控制信号和存储器事务共享。

公开(公告)号：US20090307433A1

公开(公告)日：2009-12-10

申请号：US12284332

申请日：2008-09-19

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F12/08 ,  G06F12/00 ,  G06F13/24

CPC classification number: G06F12/0862 ,  G06F12/0846 ,  G06F12/0853 ,  G06F12/0895 ,  G06F2212/6024 ,  G06F2212/6028

Abstract: Systems and methods for pre-fetching data are disclosed that use a cache memory for storing a copy of data stored in a system memory and mechanism to initiate a pre-fetch of data from the system memory into the cache memory. The system further comprises an event monitor for monitoring events that is connected to a path on which signals representing an event are transmitted between one or more event generating modules and a processor. In some embodiments, the event monitor initiates a pre-fetch of a portion of data in response to the event monitor detecting an event indicating the availability of the portion of data in the system memory.

Abstract translation: 公开了用于预取数据的系统和方法，其使用高速缓冲存储器来存储存储在系统存储器中的数据副本和机制，以发起从系统存储器预取数据到高速缓冲存储器中。 该系统还包括事件监视器，用于监视连接到一个路径上的事件，在该路径上，在一个或多个事件生成模块和处理器之间传送表示事件的信号。 在一些实施例中，响应于事件监视器检测指示系统存储器中的数据部分的可用性的事件，事件监视器启动对部分数据的预取。

公开(公告)号：US20090132750A1

公开(公告)日：2009-05-21

申请号：US12284336

申请日：2008-09-19

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/0846 ,  G06F12/0853 ,  G06F12/0895 ,  G06F2212/6024 ,  G06F2212/6028

Abstract: The present disclosure provides systems and methods for a cache memory and a cache load circuit. The cache load circuit is capable of retrieving a portion of data from the system memory and of storing a copy of the retrieved portion of data in the cache memory. In addition, the systems and methods comprise a monitoring circuit for monitoring accesses to data in the system memory.

Abstract translation: 本公开提供了用于高速缓冲存储器和高速缓存负载电路的系统和方法。 高速缓存加载电路能够从系统存储器检索一部分数据，并将所检索的部分数据的副本存储在高速缓冲存储器中。 此外，系统和方法包括用于监视对系统存储器中的数据的访问的监视电路。

公开(公告)号：US20070262653A1

公开(公告)日：2007-11-15

申请号：US11682230

申请日：2007-03-05

Applicant: Stuart Ryan ,  Andrew Jones

Inventor： Stuart Ryan ,  Andrew Jones

IPC: G06F13/00

CPC classification number: G06F11/004 ,  Y10T307/911

Abstract: An integrated circuit of the type comprises a plurality of units that may act as initiators and targets. At least some of the units are for a first purpose such as a cable modem function and others are for a second purpose such as television data processing. The units are connected together by a interconnect comprising a number of nodes. One of the nodes is configurable such that requests made from initiator units on one side of the node to target units on the other side of the node are not sent to the target units. The units for the first purpose are arranged on the opposite side of the node from those of the second purpose, so that the circuit is effectively configurable into two separate logical partitions, one partition for television data processing and the other partition for cable modem functions.

Abstract translation: 该类型的集成电路包括可用作发起者和目标的多个单元。 至少一些单元是用于电缆调制解调器功能的第一目的，而其他单元用于第二目的，例如电视数据处理。 这些单元通过包括多个节点的互连连接在一起。 节点之一是可配置的，使得从节点一侧的发起者单元到节点另一侧的目标单元的请求不发送到目标单元。 用于第一目的的单元被布置在与第二目的的节点的相对侧上，使得电路被有效地配置成两个单独的逻辑分区，用于电视数据处理的一个分区和用于电缆调制解调器功能的另一个分区。

公开(公告)号：US20130031347A1

公开(公告)日：2013-01-31

申请号：US13560294

申请日：2012-07-27

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F9/00

CPC classification number: G06F9/4403 ,  G06F12/0638

Abstract: A first arrangement including an interface configured to receive transactions with an address from a second arrangement having a first memory space; a translator configured to translate an address of a first type of received transaction to a second memory space of the first arrangement, the second memory space being different to the first memory space; and boot logic configured to map a boot transaction of the received transactions to a boot region in the second memory space.

Abstract translation: 一种第一装置，包括配置成从具有第一存储器空间的第二装置接收具有地址的事务的接口; 翻译器，被配置为将第一类型的接收到的事务的地址转换到第一布置的第二存储器空间，第二存储器空间不同于第一存储器空间; 以及引导逻辑，被配置为将所接收的事务的引导事务映射到所述第二存储器空间中的引导区域。