公开(公告)号：US5331597A

公开(公告)日：1994-07-19

申请号：US677450

申请日：1991-03-29

申请人： Sumio Tanaka

发明人： Sumio Tanaka

IPC分类号： G11C7/06 ,  G11C16/28 ,  G11C11/407

CPC分类号： G11C7/062 ,  G11C16/28

摘要： A semiconductor nonvolatile memory apparatus is composed of differential cells in which data can be written electrically, data reading sense amplifiers for reading data from these cells, and threshold voltage shift checking sense amplifier connected to respective sense inputs of the sense amplifiers through selecting switching elements and checking threshold voltages of respective transistors within the differential type cells. According to this semiconductor nonvolatile memory apparatus, data can be read out at high speed without increasing the chip size.

摘要翻译： 半导体非易失性存储装置由数据可以被写入的差分单元组成，用于从这些单元读取数据的数据读出读出放大器和通过选择开关元件连接到感测放大器的各个感测输入的阈值电压偏移检查读出放大器， 检查差分型电池内各晶体管的阈值电压。 根据该半导体非易失性存储装置，可以高速读出数据，而不增加芯片尺寸。

公开(公告)号：US5229963A

公开(公告)日：1993-07-20

申请号：US740665

申请日：1991-08-02

申请人： Nobuaki Ohtsuka ,  Sumio Tanaka ,  Junichi Miyamoto ,  Shigeru Atsumi

发明人： Nobuaki Ohtsuka ,  Sumio Tanaka ,  Junichi Miyamoto ,  Shigeru Atsumi

IPC分类号： G11C16/24

CPC分类号： G11C16/24

摘要： A nonvolatile semiconductor memory device comprising a power source terminal and a P-channel MOS transistor. A low power-source voltage is applied to the terminal during a read period. The source of the P-channel MOS transistor is coupled to the power source terminal. The conduction of the MOS transistor is controlled by data-writing operation. The drain of the MOS transistor is connected by a node to a plurality of bit lines. The device further comprises a plurality of memory cells and a plurality of N-channel MOS transistor. The memory cells have double-gate structure, each having a source coupled to the ground and a drain coupled to the corresponding bit line. Each N-channel MOS transistor has a source and a drain connected to the ground and the corresponding bit line, respectively, for discharging the bit line. Each N-channel MOS transistor is rendered conductive temporarily when the supply of the high power source voltage to the power source terminal is started, whereby the potential of the corresponding bit line is decreased. The bit-line potential is decreased sufficiently since the P-channel MOS transistors have a conductance greater than that of any other transistor incorporated in the device.

摘要翻译： 一种非易失性半导体存储器件，包括电源端子和P沟道MOS晶体管。 在读取期间，向终端施加低电源电压。 P沟道MOS晶体管的源极耦合到电源端子。 通过数据写入操作来控制MOS晶体管的导通。 MOS晶体管的漏极由节点连接到多个位线。 该器件还包括多个存储单元和多个N沟道MOS晶体管。 存储单元具有双栅极结构，每个具有耦合到地的源极和耦合到相应位线的漏极。 每个N沟道MOS晶体管的源极和漏极分别连接到地和对应的位线，用于对位线进行放电。 当向电源端子供给高电源电压时，每个N沟道MOS晶体管暂时导通，从而相应位线的电位降低。 因为P沟道MOS晶体管的电导率大于装在器件中的任何其他晶体管的电导率，所以位线电位被充分降低。

公开(公告)号：US4467225A

公开(公告)日：1984-08-21

申请号：US183814

申请日：1980-09-03

申请人： Sumio Tanaka

发明人： Sumio Tanaka

IPC分类号： G11C11/41 ,  G11C8/10 ,  G11C11/413 ,  H02J1/00 ,  H03K3/01 ,  H03K17/687 ,  H03K19/094

CPC分类号： G11C8/10

摘要： An address selection device comprising an address buffer for receiving an address selection signal to produce an output signal which is complementary to the address selection signal; and a decoder circuit for decoding the address selection signal which includes a plurality of MOS transistors connected in parallel with one another and for receiving at their gates corresponding address bit signals of the address selection signal, a MOS transistor as a load resistor connected in series with said plurality of MOS transistors, and a MOS transistor connected between the load resistor MOS transistor and a power source terminal for operating a power source switch and for receiving at the gate a specified bit signal of the complementary signal applied from the address buffer.

摘要翻译： 一种地址选择装置，包括地址缓冲器，用于接收地址选择信号以产生与地址选择信号互补的输出信号; 以及解码电路，用于解码地址选择信号，该地址选择信号包括彼此并联连接的多个MOS晶体管，并且用于在其门上接收与地址选择信号相对应的地址位信号，MOS晶体管作为负载电阻串联连接 所述多个MOS晶体管和MOS晶体管连接在负载电阻MOS晶体管和用于操作电源开关的电源端子之间，并用于在栅极处接收从地址缓冲器施加的互补信号的指定位信号。

公开(公告)号：US4453174A

公开(公告)日：1984-06-05

申请号：US152292

申请日：1980-05-22

申请人： Yuichi Kawasaki ,  Sumio Tanaka ,  Hiroshi Iwahashi ,  Masamichi Asano ,  Shinichi Maekawa ,  Masazi Mito

发明人： Yuichi Kawasaki ,  Sumio Tanaka ,  Hiroshi Iwahashi ,  Masamichi Asano ,  Shinichi Maekawa ,  Masazi Mito

IPC分类号： H01L21/76 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/088 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792 ,  H01L29/02

CPC分类号： G11C16/0416 ,  H01L27/088 ,  H01L27/105

摘要： Disclosed is a metal oxide semiconductor integrated circuit device having an array of electrically rewritable, insulated gate type non-volatile semiconductor memory cells formed on a semiconductor substrate, read/write mode setting circuit and address designating circuits arranged corresponding to the memory cell array, those circuits being fabricated on the substrate, and a field insulating layer formed on the substrate. A cut portion is formed in the field insulating layer to surround the memory cell array.

摘要翻译： 公开了一种金属氧化物半导体集成电路器件，其具有形成在半导体衬底上的电可重写绝缘栅型非易失性半导体存储单元阵列，读/写模式设置电路和对应于存储单元阵列布置的地址指定电路 在衬底上制造的电路和形成在衬底上的场绝缘层。 在场绝缘层中形成切割部分以包围存储单元阵列。

公开(公告)号：US07295456B2

公开(公告)日：2007-11-13

申请号：US11382098

申请日：2006-05-08

申请人： Ryu Ogiwara ,  Daisaburo Takashima ,  Sumio Tanaka ,  Yukihito Oowaki ,  Yoshiaki Takeuchi

发明人： Ryu Ogiwara ,  Daisaburo Takashima ,  Sumio Tanaka ,  Yukihito Oowaki ,  Yoshiaki Takeuchi

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

摘要翻译： 链式铁电随机存取存储器具有包括彼此串联电连接的铁电存储单元的存储单元单元，连接到存储单元单元的电极的板线，连接到存储单元单元的另一个电极的位线 通过开关晶体管，放大该位线及其互补位线的电压的读出放大器以及插在开关晶体管和读出放大器之间的晶体管。 作为板线电压和比较放大的升压期间获得的晶体管中的栅极电压的最小值的值小于在板线掉电期间获得的晶体管中的栅极电压的最大值 电压和比较放大。 利用这些特征，存储单元中的累积电荷的减小减少，并且在读/写操作期间阻止了干扰的发生。

公开(公告)号：US6166987A

公开(公告)日：2000-12-26

申请号：US443100

申请日：1999-11-18

申请人： Shigeru Atsumi ,  Sumio Tanaka

发明人： Shigeru Atsumi ,  Sumio Tanaka

IPC分类号： G11C17/00 ,  G11C7/00 ,  G11C8/00 ,  G11C8/08 ,  G11C16/06 ,  G11C16/08 ,  G11C16/14 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115

CPC分类号： G11C8/08 ,  G11C16/08 ,  G11C16/14

摘要： A nonvolatile semiconductor memory device is provided in which a negative voltage is applied to a gate electrode of a memory cell transistor during an erase mode. The memory device includes a row decoder circuit having an N-channel transistor connected to a word line. The N-channel transistor is provided on a P-type well region of a semiconductor substrate. A negative voltage is applied to the P-type well region during the erase mode, while ground potential is applied thereto during another modes.

摘要翻译： 提供了一种非易失性半导体存储器件，其中在擦除模式期间将负电压施加到存储单元晶体管的栅电极。 存储器件包括具有连接到字线的N沟道晶体管的行解码器电路。 N沟道晶体管设置在半导体衬底的P型阱区上。 在擦除模式期间，向P型阱区施加负电压，而在其它模式期间施加接地电位。

公开(公告)号：US6111777A

公开(公告)日：2000-08-29

申请号：US401663

申请日：1999-09-23

申请人： Ryu Ogiwara ,  Sumio Tanaka

发明人： Ryu Ogiwara ,  Sumio Tanaka

IPC分类号： G11C14/00 ,  G11C11/22 ,  H01L27/10

CPC分类号： G11C11/22

摘要： A dummy cell is provided in every column and consists of a dummy capacitor and two transistors. When the charge of the ferroelectric capacitor is released to one of a bit line pair, a first dummy word line is selected and charge of the dummy capacitor is released to the other of the bit line pair by way of one of the two transistors. When the charge of the ferroelectric capacitor is released to the other of the bit line pair, a second dummy word line is selected and the charge of the dummy capacitor is released to one of the bit line pair by way of the other one of the two transistors. When either one of the first and second dummy word lines is selected the dummy plate driver supplies a clock signal to the dummy capacitor.

摘要翻译： 每个列提供一个虚拟单元，由虚拟电容器和两个晶体管构成。 当铁电电容器的电荷被释放到位线对中的一个时，选择第一虚拟字线，并且通过两个晶体管之一将虚拟电容器的电荷释放到位线对中的另一个。 当铁电电容器的电荷释放到位线对中的另一个时，选择第二虚拟字线，并且虚拟电容器的电荷通过两个位线对中的另一个被释放到位线对中的一个 晶体管。 当选择第一和第二虚拟字线中的任何一个时，虚拟板驱动器向虚拟电容器提供时钟信号。

公开(公告)号：US5875129A

公开(公告)日：1999-02-23

申请号：US744821

申请日：1996-11-06

申请人： Shigeru Atsumi ,  Sumio Tanaka

发明人： Shigeru Atsumi ,  Sumio Tanaka

IPC分类号： H01L21/8247 ,  G11C16/08 ,  G11C16/30 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

CPC分类号： G11C16/30 ,  G11C16/08 ,  H01L27/105

摘要： In a flash memory EEPROM, a memory cell MC is formed in a P-type semiconductor substrate. A peripheral transistor TR is formed in an N-type well. Another peripheral transistor TR is formed in a P-type well. The P-type well is by turn formed an N-type well and electrically insulated from the substrate. The substrate is typically provided with a metal back structure and its substrate voltage is set to predetermined voltages respectively for data erasure, data storage and data retrieval. With such an arrangement, the level of voltage stress with which the device is loaded during data erasure can be remarkably reduced to allow a down-sizing and an enhanced quality to be realized for the device.

摘要翻译： 在闪速存储器EEPROM中，在P型半导体衬底中形成存储单元MC。 外围晶体管TR形成在N型阱中。 另一个外围晶体管TR形成在P型阱中。 P型阱依次形成N型阱并与衬底电绝缘。 基板通常设置有金属背部结构，并且其基板电压分别设置为预定电压用于数据擦除，数据存储和数据检索。 通过这样的布置，可以显着地减少在数据擦除期间装载装置的电压应力的水平，以允许对装置实现缩小尺寸和增强的质量。

公开(公告)号：US5265061A

公开(公告)日：1993-11-23

申请号：US943145

申请日：1992-09-10

申请人： Sumio Tanaka

发明人： Sumio Tanaka

IPC分类号： G11C7/14 ,  G11C17/12 ,  G11C7/00 ,  G11C11/40 ,  H03K19/003 ,  H03K19/0175

CPC分类号： G11C17/12 ,  G11C7/14

摘要： A semiconductor non-volatile memory device having non-volatile memory cells for storing binary data, a plurality of column lines respectively connected to the plurality of memory cells and a plurality of row lines respectively connected to the plurality of memory cells comprising a plurality of dummy cells, having the same structure as the memory cells, respectively connected to the column lines and arranged to be set in an ON state upon being selected, a dummy row line connected to the plurality of dummy cells, a dummy row line selector for selecting the dummy row line for a predetermined period in response to a chip selection signal for selecting the memory device. Therefore, since the dummy row line is selected for the predetermined period before the memory device is selected by a computer system or the like, each of the column lines is set at a ground potential by a dummy memory cell set in an ON state. During a transition from the non-selected state to a selected state of the memory device, in synchronism with the transition from the non-selected state to the selected state of a target memory cell in a plurality of memory cells, the state of a dummy cell connected to the target memory cell transits from the selected state to the non-selected state.

摘要翻译： 一种具有用于存储二进制数据的非易失性存储单元的半导体非易失性存储器件，分别连接到多个存储器单元的多个列线以及分别连接到多个存储器单元的多个行线，包括多个虚拟 单元，具有与存储单元相同的结构，分别连接到列线并被布置为在选择时被设置为ON状态，连接到多个虚设单元的虚拟行线，用于选择 响应于用于选择存储器件的芯片选择信号，预定周期的虚拟行线。 因此，由于在通过计算机系统等选择存储器件之前的预定时段内选择了虚拟行线，所以通过设置在ON状态的虚拟存储器单元将每条列线设置为接地电位。 在从非选择状态到存储器件的选择状态的转变期间，与从多个存储器单元中的目标存储器单元从未选择状态到选定状态的转换同步，虚拟的状态 连接到目标存储器单元的单元从所选状态转换到未选择状态。

公开(公告)号：US5237534A

公开(公告)日：1993-08-17

申请号：US854793

申请日：1992-03-23

申请人： Sumio Tanaka ,  Toshiyuki Sanko

发明人： Sumio Tanaka ,  Toshiyuki Sanko

IPC分类号： G11C16/04 ,  G11C16/28

CPC分类号： G11C16/0441 ,  G11C16/28

摘要： The current paths of column selection transistors are inserted between a pair of input nodes, on the one hand, of a sense amplifier constituted by a current-mirror type differential amplifier, and column lines, on the other hand. The current paths of transistors for clamping column potential are inserted between the input nodes of the sense amplifier, on the one hand, and a power source, on the other. The gates of the transistors for clamping column potential are supplied with a bias potential lower than the potential of the power source. When data is read out from selected memory cells, the potential of the input nodes of the sense amplifier is clamped to a value lower than the potential Vcc of the power source by the transistors for clamping column potential. The storage data in the selected memory cells is input directly to the input nodes of the sense amplifier through the current paths of the column selection transistors.

摘要翻译： 另一方面，列选择晶体管的电流路径插入在一对输入节点之间，一方面由电流镜型差分放大器构成的读出放大器和列线。 用于钳位列电势的晶体管的电流路径一方面插入在读出放大器的输入节点和另一端的电源之间。 用于钳位列电位的晶体管的栅极被提供有低于电源电位的偏置电位。 当从所选择的存储单元中读出数据时，读出放大器的输入节点的电位被钳位在用于钳位列电位的晶体管的电压低于电源的电位Vcc。 所选存储单元中的存储数据通过列选择晶体管的电流路径直接输入到读出放大器的输入节点。