公开(公告)号：US20090049219A1

公开(公告)日：2009-02-19

申请号：US11658816

申请日：2005-08-19

申请人： Hideshi Nishida ,  Takeshi Furuta ,  Tetsuya Tanaka ,  Kozo Kimura ,  Tokuzo Kiyohara

发明人： Hideshi Nishida ,  Takeshi Furuta ,  Tetsuya Tanaka ,  Kozo Kimura ,  Tokuzo Kiyohara

IPC分类号： G06F13/24

CPC分类号： G06F13/24 ,  G06F9/30101 ,  G06F9/3861 ,  G06F9/3879 ,  G06F9/4812 ,  G06F2209/481

摘要： To provide an information processing apparatus capable of performing switching between an exception handler and normal processing, the information processing apparatus comprising: An information processing apparatus comprising: a processor; a data processing unit operable to perform particular processing upon receiving a processing request from the processor; an interrupt controller operable to issue an interrupt request to the processor; and an exception control unit operable to control the interrupt controller, wherein the data processing unit is connected with the exception control unit via a dedicated line, the data processing unit includes a notification unit operable to notify, via the dedicated line, the exception control unit of status information showing a current status of the data processing unit, and based on the notified status information and setup information set by the processor, the exception control unit judges whether to cause the interrupt controller to issue an interrupt request to execute an exception handler to the processor.

摘要翻译： 为了提供能够执行异常处理程序与正常处理之间的切换的信息处理装置，所述信息处理装置包括：信息处理装置，包括：处理器; 数据处理单元，用于在从所述处理器接收到处理请求时执行特定处理; 中断控制器，用于向所述处理器发出中断请求; 以及异常控制单元，其可操作以控制所述中断控制器，其中所述数据处理单元经由专用线与所述异常控制单元连接，所述数据处理单元包括通知单元，用于经由所述专用线通知所述异常控制单元 表示数据处理单元的当前状态的状态信息，并且基于所通知的状态信息和由处理器设置的设置信息，异常控制单元判断是否使中断控制器发出中断请求以执行异常处理程序 处理器。

公开(公告)号：US20090037916A1

公开(公告)日：2009-02-05

申请号：US11574359

申请日：2006-04-12

申请人： Hiroyuki Morishita ,  Takashi Hashimoto ,  Tokuzo Kiyohara

发明人： Hiroyuki Morishita ,  Takashi Hashimoto ,  Tokuzo Kiyohara

IPC分类号： G06F9/46

CPC分类号： G06F15/7867 ,  G06F9/30076 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/3885 ,  G06F9/3897

摘要： The present invention provides a processor that cyclically executes a plurality of threads in accordance with an execution time allocated to each of the threads, comprising a reconfigurable integrated circuit. The processor stores circuit configuration information sets respectively corresponding to the plurality of threads, reconfigures a part of the integrated circuit based on the circuit configuration information sets, and sequentially executes each thread using the integrated circuit that has been reconfigured based on one of the configuration information sets that corresponds to the thread. While executing a given thread, the processor selects a thread to be executed next, and reconfigures a part of the integrated circuit where is not currently used for execution of the given thread, based on a circuit configuration information set corresponding to the selected thread.

摘要翻译： 本发明提供了一种根据分配给每个线程的执行时间循环地执行多个线程的处理器，包括可重构集成电路。 处理器存储分别对应于多个线程的电路配置信息集，基于电路配置信息集重配置集成电路的一部分，并且使用基于配置信息之一重新配置的集成电路来顺序地执行每个线程 设置对应于线程。 在执行给定的线程的同时，处理器根据与所选择的线程对应的电路配置信息，选择要执行的线程，并重新配置当前不用于执行给定线程的集成电路的一部分。

公开(公告)号：US20080215782A1

公开(公告)日：2008-09-04

申请号：US11629164

申请日：2005-06-20

申请人： Tetsuji Mochida ,  Tokuzo Kiyohara ,  Takashi Yamada

发明人： Tetsuji Mochida ,  Tokuzo Kiyohara ,  Takashi Yamada

IPC分类号： G06F13/372

CPC分类号： G06F13/1605

摘要： An arbitration device arbitrates among master devices such that each master device is allowed to access a shared memory at a predetermined bandwidth, and the arbitration device permits an access request in a first period that a designer has set as desired if the access request has been made by a specific master device beyond a bandwidth that has been allocated in advance. The arbitration device masks an access request from the specific master device in a second period that follows the first period.

摘要翻译： 仲裁装置在主设备之间进行仲裁，使得允许每个主设备以预定带宽访问共享存储器，并且仲裁设备允许设计者在已经设置了访问请求的第一时段中设置访问请求 通过特定的主设备超出已预先分配的带宽。 仲裁设备在跟随第一周期的第二周期中屏蔽来自特定主设备的访问请求。

公开(公告)号：US07395410B2

公开(公告)日：2008-07-01

申请号：US11172601

申请日：2005-06-30

申请人： Masaki Maeda ,  Hiroyuki Morishita ,  Takeshi Tanaka ,  Tokuzo Kiyohara

发明人： Masaki Maeda ,  Hiroyuki Morishita ,  Takeshi Tanaka ,  Tokuzo Kiyohara

IPC分类号： G06F15/16

CPC分类号： G06F9/3877 ,  G06F9/3885

摘要： A processor system includes a main processor having registers and an instruction decode control unit, and a coprocessor. When the main processor performs an operation in accordance with an instruction, the registers store data to be used for the operation and data obtained by the operation, and the control unit sequentially decodes an instruction, and performs a control based on the instruction. When decoding a coprocessor operation instruction to request the coprocessor to perform an operation, which includes operands designating a type of an operation to be performed by the coprocessor, a first register storing data to be used for the operation, and a second register to store data obtained by the operation, the control unit requests the coprocessor to perform the designated type of operation by using a content in the first register, and causes the second register to store a result of the operation.

摘要翻译： 处理器系统包括具有寄存器和指令解码控制单元的主处理器以及协处理器。 当主处理器根据指令执行操作时，寄存器存储要用于操作的数据和通过操作获得的数据，并且控制单元顺序地解码指令，并且基于该指令进行控制。 当解码协处理器操作指令以请求协处理器执行操作时，其包括指定要由协处理器执行的操作的类型的操作数，存储要用于操作的数据的第一寄存器和用于存储数据的第二寄存器 通过该操作获得，控制单元通过使用第一寄存器中的内容来请求协处理器执行指定类型的操作，并且使第二寄存器存储操作的结果。

公开(公告)号：US20080101473A1

公开(公告)日：2008-05-01

申请号：US11923779

申请日：2007-10-25

申请人： Takeshi TANAKA ,  Tokuzo KIYOHARA

发明人： Takeshi TANAKA ,  Tokuzo KIYOHARA

IPC分类号： H04N7/26

CPC分类号： H04N19/112 ,  H04N19/159 ,  H04N19/16 ,  H04N19/176 ,  H04N19/40 ,  H04N19/426 ,  H04N19/46 ,  H04N19/523 ,  H04N19/56 ,  H04N19/61

摘要： A transcoding apparatus and a transcoding method convert MPEG-2 compressed video to H.264 compressed video without increasing the circuit size while also preventing loss of image quality. The transcoding apparatus has a transcoder. The transcoder has an MPEG-2 decoder for decoding an MPEG-2 video stream, a data transform unit, and a H.264 encoder. The data transform unit converts the header information, macroblock information, and motion vector information of the macroblocks in the decoded MPEG-2 video stream to the header information, macroblock information, and motion vector information of H.264 macroblocks. The H.264 encoder encodes the MPEG-2 video stream as an H.264 video stream based on the converted information.

摘要翻译： 代码转换装置和代码转换方法将MPEG-2压缩视频转换为H.264压缩视频，而不增加电路大小，同时也防止图像质量的损失。 代码转换装置具有代码转换器。 代码转换器具有用于解码MPEG-2视频流的MPEG-2解码器，数据变换单元和H.264编码器。 数据变换单元将解码的MPEG-2视频流中的宏块的头信息，宏块信息和运动矢量信息转换为H.264宏块的头信息，宏块信息和运动矢量信息。 H.264编码器基于转换的信息将MPEG-2视频流编码为H.264视频流。

公开(公告)号：US20080046687A1

公开(公告)日：2008-02-21

申请号：US11896368

申请日：2007-08-31

申请人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Tsuneyuki Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Masaki Maeda

发明人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Tsuneyuki Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Masaki Maeda

IPC分类号： G06F9/302 ,  G06F15/80

CPC分类号： G06F9/30025 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167

摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.

公开(公告)号：US07259989B2

公开(公告)日：2007-08-21

申请号：US11204316

申请日：2005-08-16

申请人： Masayuki Toyama ,  Tokuzo Kiyohara

发明人： Masayuki Toyama ,  Tokuzo Kiyohara

IPC分类号： G11C16/04

CPC分类号： G11C16/20 ,  G11C7/1015 ,  G11C7/1045 ,  G11C16/06

摘要： A non-volatile memory device is disclosed that can reduce the time required for the initialization process. A non-volatile memory device includes a non-volatile memory array having a plurality of pages. Each page includes a plurality of non-volatile memory cells, a first region for storing data, and a second region for storing control data that is associated with the data of the first region. The non-volatile memory device further includes a read out unit for reading out data from the pages, and a data buffer for temporarily storing data that has been read out from the pages by the read out unit. When reading out the control data, the read out unit reads out the second regions, across a plurality of pages, at one time.

摘要翻译： 公开了可以减少初始化过程所需时间的非易失性存储器件。 非易失性存储器件包括具有多页的非易失性存储器阵列。 每个页面包括多个非易失性存储器单元，用于存储数据的第一区域和用于存储与第一区域的数据相关联的控制数据的第二区域。 非易失性存储装置还包括用于从页面读出数据的读出单元和用于临时存储由读出单元从页面读出的数据的数据缓冲器。 当读出控制数据时，读出单元一次读出多个页面中的第二区域。

公开(公告)号：US20060010305A1

公开(公告)日：2006-01-12

申请号：US11172601

申请日：2005-06-30

申请人： Masaki Maeda ,  Hiroyuki Morishita ,  Takeshi Tanaka ,  Tokuzo Kiyohara

发明人： Masaki Maeda ,  Hiroyuki Morishita ,  Takeshi Tanaka ,  Tokuzo Kiyohara

IPC分类号： G06F15/00

CPC分类号： G06F9/3877 ,  G06F9/3885

摘要： A processor system includes a main processor having registers and an instruction decode control unit, and a coprocessor. When the main processor performs an operation in accordance with an instruction, the registers store data to be used for the operation and data obtained by the operation, and the control unit sequentially decodes an instruction, and performs a control based on the instruction. When decoding a coprocessor operation instruction to request the coprocessor to perform an operation, which includes operands designating a type of an operation to be performed by the coprocessor, a first register storing data to be used for the operation, and a second register to store data obtained by the operation, the control unit requests the coprocessor to perform the designated type of operation by using a content in the first register, and causes the second register to store a result of the operation.

摘要翻译： 处理器系统包括具有寄存器和指令解码控制单元的主处理器以及协处理器。 当主处理器根据指令执行操作时，寄存器存储要用于操作的数据和通过操作获得的数据，并且控制单元顺序地解码指令，并且基于该指令进行控制。 当解码协处理器操作指令以请求协处理器执行操作时，其包括指定要由协处理器执行的操作的类型的操作数，存储要用于操作的数据的第一寄存器和用于存储数据的第二寄存器 通过该操作获得，控制单元通过使用第一寄存器中的内容来请求协处理器执行指定类型的操作，并且使第二寄存器存储操作的结果。

公开(公告)号：US06901454B2

公开(公告)日：2005-05-31

申请号：US10289993

申请日：2002-11-07

申请人： Nobuo Higaki ,  Tetsuya Tanaka ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura ,  Hideshi Nishida

发明人： Nobuo Higaki ,  Tetsuya Tanaka ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura ,  Hideshi Nishida

IPC分类号： G06F9/38 ,  G06F3/00 ,  G06F9/46 ,  G06F9/48 ,  G06F13/28 ,  G06F15/16 ,  G06F15/167 ,  G06F15/80

CPC分类号： G06F9/4843

摘要： A circuit group control system which receives from a master processor a first command sequence and a second command sequence each of which is composed of a plurality of commands, each command being to be executed by one of a plurality of circuits, and causes any available circuits to execute the commands one by one in order of arrangement in each command sequence. The circuit group control system achieves concurrent execution of a plurality of command sequences by causing a circuit (a second circuit) to execute a command in the second command sequence while another circuit (a first circuit) is executing another command in the first command sequence.

摘要翻译： 一种电路组控制系统，其从主处理器接收第一命令序列和第二命令序列，每个命令序列由多个命令组成，每个命令由多个电路中的一个执行，并且使任何可用的电路 按照每个命令序列中的排列顺序逐个执行命令。 电路组控制系统通过使电路（第二电路）在第二命令序列中执行命令而实现多个命令序列的并发执行，而另一电路（第一电路）在第一命令序列中执行另一命令。

公开(公告)号：US06829302B2

公开(公告)日：2004-12-07

申请号：US10019498

申请日：2001-12-20

申请人： Hiroyuki Morishita ,  Kosuke Yoshioka ,  Hideshi Nishida ,  Makoto Hirai ,  Ryuji Matsuura ,  Toshiaki Tsuji ,  Kozo Kimura ,  Tokuzo Kiyohara

发明人： Hiroyuki Morishita ,  Kosuke Yoshioka ,  Hideshi Nishida ,  Makoto Hirai ,  Ryuji Matsuura ,  Toshiaki Tsuji ,  Kozo Kimura ,  Tokuzo Kiyohara

IPC分类号： H04N712

CPC分类号： H04N19/80 ,  G06T3/4007 ,  G06T3/4023 ,  G06T5/20 ,  G06T2200/28

摘要： A pixel calculating device that performs vertical filtering on pixel data in order to reduce frame data in a vertical direction. The pixel calculating device includes a decoding unit 401 for decoding compressed video data to produce frame data, frame memory 402 for storing the frame data, a filtering unit 403 for reducing the frame data in a vertical direction by the vertical filtering to produce a reduced image, buffer memory 404 for storing the reduced image outputted from filtering unit 403, and a control unit 406 for controlling filtering unit 403 based on a decoding state of the video data by decoding unit 401 and a filtering state of the frame data by filtering unit 403, so that overrun and underrun do not occur in filtering unit 403.

摘要翻译： 一种对像素数据进行垂直滤波以便在垂直方向上减少帧数据的像素计算装置。 像素计算装置包括用于解码压缩视频数据以产生帧数据的解码单元401，用于存储帧数据的帧存储器402，用于通过垂直滤波减少垂直方向上的帧数据以产生缩小图像的滤波单元403 用于存储从滤波单元403输出的缩小图像的缓冲存储器404，以及基于解码单元401的视频数据的解码状态和滤波单元403的帧数据的滤波状态来控制滤波单元403的控制单元406 ，因此在过滤单元403中不会发生溢出和欠载。