公开(公告)号：US6016201A

公开(公告)日：2000-01-18

申请号：US135435

申请日：1998-08-17

Applicant: Chin-Lung Lin ,  Yao-Ching Ku

Inventor： Chin-Lung Lin ,  Yao-Ching Ku

IPC: G01N21/956 ,  G01B11/00

CPC classification number: G01N21/95607

Abstract: An inspection method for a correction pattern includes the following steps. An optical proximity correction is performed to an original pattern to obtain an optical proximity correction pattern. An "exclusive or" logic operation is done to the original pattern and the optical correction pattern to obtain an inspection pattern. The inspection pattern includes a number of kinds of line width sizing. The line width sizing of the inspection pattern is then compared with an optical correction reference size.

Abstract translation: 校正图案的检查方法包括以下步骤。 对原始图案进行光学邻近校正以获得光学邻近校正图案。 对原始图案和光学校正图案进行“异或”逻辑运算以获得检查图案。 检查图案包括多种线宽尺寸。 然后将检查图案的线宽尺寸与光学校正参考尺寸进行比较。

公开(公告)号：US20120146159A1

公开(公告)日：2012-06-14

申请号：US13293650

申请日：2011-11-10

Applicant: Hsien-Cheng WANG ,  Ming-Chang WEN ,  Chun-Kuang CHEN ,  Yao-Ching KU

Inventor： Hsien-Cheng WANG ,  Ming-Chang WEN ,  Chun-Kuang CHEN ,  Yao-Ching KU

IPC: H01L29/78 ,  H01L21/66 ,  H01L21/336

CPC classification number: H01L22/32 ,  G03F7/70633 ,  H01L21/265 ,  H01L29/517 ,  H01L29/66545

Abstract: The overlay mark and method for making the same are described. In one embodiment, a semiconductor overlay structure includes gate stack structures formed on the semiconductor substrate and configured as an overlay mark, and a doped semiconductor substrate disposed on both sides of the gate stack structure that includes at least as much dopant as the semiconductor substrate adjacent to the gate stack structure in a device region. The doped semiconductor substrate is formed by at least three ion implantation steps.

Abstract translation: 对覆盖标记及其制作方法进行说明。 在一个实施例中，半导体覆盖结构包括形成在半导体衬底上并被配置为覆盖标记的栅极叠层结构，以及设置在栅叠层结构两侧的掺杂半导体衬底，其至少包括与半导体衬底相邻的掺杂剂 到设备区域中的栅极堆栈结构。 掺杂半导体衬底通过至少三个离子注入步骤形成。

公开(公告)号：US08001494B2

公开(公告)日：2011-08-16

申请号：US12250424

申请日：2008-10-13

Applicant: Yung-Chin Hou ,  Ying-Chou Cheng ,  Ru-Gun Liu ,  Chih-Ming Lai ,  Yi-Kan Cheng ,  Chung-Kai Lin ,  Hsiao-Shu Chao ,  Ping-Heng Yeh ,  Min-Hong Wu ,  Yao-Ching Ku ,  Tsong-Hua Ou

Inventor： Yung-Chin Hou ,  Ying-Chou Cheng ,  Ru-Gun Liu ,  Chih-Ming Lai ,  Yi-Kan Cheng ,  Chung-Kai Lin ,  Hsiao-Shu Chao ,  Ping-Heng Yeh ,  Min-Hong Wu ,  Yao-Ching Ku ,  Tsong-Hua Ou

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5081

Abstract: Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.

Abstract translation: 公开了一种用于集成电路设计和后期布局分析的系统和方法。 集成电路设计方法包括提供具有各种设计尺寸的多个IC器件; 收集IC器件的电气性能数据; 提取IC器件的等效尺寸; 产生形状相关模型以将等效尺寸与IC器件的电性能数据相关联; 以及使用等效尺寸和电气性能数据创建数据细化表。

公开(公告)号：US07727682B2

公开(公告)日：2010-06-01

申请号：US11689242

申请日：2007-03-21

Applicant: Hung-Ting Pan ,  Ken Wu ,  Luke Hsu ,  Yao-Ching Ku

Inventor： Hung-Ting Pan ,  Ken Wu ,  Luke Hsu ,  Yao-Ching Ku

IPC: G03F1/00

CPC classification number: G03F1/62 ,  G03F1/26 ,  G03F1/48 ,  G03F1/86

Abstract: System and method for providing a passivation layer for a phase shift mask (“PSM”) are described. In one embodiment, a PSM comprises a transparent substrate; a phase shift pattern disposed on the transparent substrate; and a passivation layer disposed to substantially cover exposed surfaces of at least a portion of the phase shift pattern.

Abstract translation: 描述了用于为相移掩模（“PSM”）提供钝化层的系统和方法。 在一个实施例中，PSM包括透明基板; 设置在所述透明基板上的相移图案; 以及钝化层，其设置成基本上覆盖至少部分相移图案的暴露表面。

公开(公告)号：US20090258159A1

公开(公告)日：2009-10-15

申请号：US12100822

申请日：2008-04-10

Applicant: Yih-Chen Su ,  Ting-Hao Hsu ,  Sheng-Chi Chin ,  Heng-Jen Lee ,  Hung Chang Hsieh ,  Yao-Ching Ku

Inventor： Yih-Chen Su ,  Ting-Hao Hsu ,  Sheng-Chi Chin ,  Heng-Jen Lee ,  Hung Chang Hsieh ,  Yao-Ching Ku

IPC: B08B6/00 ,  B05D3/06

CPC classification number: G03F1/82

Abstract: A method includes forming an absorption material layer on a mask; applying a plasma treatment to the mask to reduce chemical contaminants after the forming of the absorption material layer; performing a chemical cleaning process of the mask; and performing a gas injection to the mask.

Abstract translation: 一种方法包括在掩模上形成吸收材料层; 对掩模施加等离子体处理以在形成吸收材料层之后减少化学污染物; 进行面罩的化学清洗处理; 并对所述面罩进行气体注入。

公开(公告)号：US20090206057A1

公开(公告)日：2009-08-20

申请号：US12031501

申请日：2008-02-14

Applicant: I-Hsiung Huang ,  Chi-Lun Lu ,  Heng-Jen Lee ,  Sheng-Chi Chin ,  Yao-Ching Ku

Inventor： I-Hsiung Huang ,  Chi-Lun Lu ,  Heng-Jen Lee ,  Sheng-Chi Chin ,  Yao-Ching Ku

IPC: C23F1/08

CPC classification number: G03F1/32 ,  G03F1/36 ,  G03F1/80 ,  H01J37/32422 ,  H01L21/67167 ,  H01L21/67207 ,  H01L21/67236

Abstract: A method and system for fabricating a substrate is disclosed. First, a plurality of process chambers are provided, at least one of the plurality of process chambers adapted to receive at least one plasma filtering plate and at least one of the plurality of process chambers containing a plasma filtering plate library. A plasma filtering plate is selected and removed from the plasma filtering plate library. Then, the plasma filtering plate is inserted into at least one of the plurality of process chambers adapted to receive at least one plasma filtering plate. Subsequently, an etching process is performed in the substrate.

Abstract translation: 公开了一种用于制造衬底的方法和系统。 首先，提供多个处理室，多个处理室中的至少一个适于接收至少一个等离子体过滤板和多个处理室中的至少一个包含等离子体过滤板库。 从等离子体过滤板文库中选择并除去等离子体过滤板。 然后，将等离子体过滤板插入适于接收至少一个等离子体过滤板的多个处理室中的至少一个。 随后，在衬底中进行蚀刻处理。

公开(公告)号：US20090187866A1

公开(公告)日：2009-07-23

申请号：US12016661

申请日：2008-01-18

Applicant: Tsong-Hua Ou ,  Ying-Chou Cheng ,  Chia-Chi Lin ,  Ru-Gun Liu ,  Chih-Ming Lai ,  Min-Hong Wu ,  Yih-Yuh Doong ,  Cliff Hou ,  Yao-Ching Ku

Inventor： Tsong-Hua Ou ,  Ying-Chou Cheng ,  Chia-Chi Lin ,  Ru-Gun Liu ,  Chih-Ming Lai ,  Min-Hong Wu ,  Yih-Yuh Doong ,  Cliff Hou ,  Yao-Ching Ku

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F17/5036 ,  G06F2217/80

Abstract: A system, method, and computer readable medium for generating a parameterized and characterized pattern library for use in extracting parasitics from an integrated circuit design is provided. In an embodiment, a layout of an interconnect pattern is provided. A process simulation may be performed on the interconnect pattern. In a further embodiment, the interconnect pattern is dissected into a plurality of segments taking into account OPC rules. A parasitic resistance and/or parasitic capacitance associated with the interconnect pattern may be determined by a physical model and/or field solver.

Abstract translation: 提供了一种用于从集成电路设计中产生用于提取寄生效应的参数化和表征的模式库的系统，方法和计算机可读介质。 在一个实施例中，提供了互连图案的布局。 可以在互连图案上执行过程模拟。 在另一实施例中，考虑到OPC规则，将互连图案解剖成多个段。 与互连图案相关联的寄生电阻和/或寄生电容可由物理模型和/或场求解器确定。

公开(公告)号：US20080233486A1

公开(公告)日：2008-09-25

申请号：US11689242

申请日：2007-03-21

Applicant: Hung-Ting Pan ,  Ken Wu ,  Luke Hsu ,  Yao-Ching Ku

Inventor： Hung-Ting Pan ,  Ken Wu ,  Luke Hsu ,  Yao-Ching Ku

IPC: G03F1/00

CPC classification number: G03F1/62 ,  G03F1/26 ,  G03F1/48 ,  G03F1/86

Abstract: System and method for providing a passivation layer for a phase shift mask (“PSM”) are described. In one embodiment, a PSM comprises a transparent substrate; a phase shift pattern disposed on the transparent substrate; and a passivation layer disposed to substantially cover exposed surfaces of at least a portion of the phase shift pattern.

Abstract translation: 描述了用于为相移掩模（“PSM”）提供钝化层的系统和方法。 在一个实施例中，PSM包括透明基板; 设置在所述透明基板上的相移图案; 以及钝化层，其设置成基本上覆盖至少部分相移图案的暴露表面。

公开(公告)号：US06492073B1

公开(公告)日：2002-12-10

申请号：US09839926

申请日：2001-04-23

Applicant: Burn Jeng Lin ,  Ru-Gun Liu ,  Shih-Ying Chen ,  Shinn-Sheng Yu ,  Hua-Tai Lin ,  Anthony Yen ,  Yao-Ching Ku

Inventor： Burn Jeng Lin ,  Ru-Gun Liu ,  Shih-Ying Chen ,  Shinn-Sheng Yu ,  Hua-Tai Lin ,  Anthony Yen ,  Yao-Ching Ku

IPC: G03F900

CPC classification number: G03F1/36 ,  G03F1/70 ,  G03F7/70433 ,  G03F7/70441

Abstract: A mask set of two masks and a method of using these masks in a double exposure to avoid line shortening due to optical proximity effects is described. A pattern having pattern elements comprising a number of line segments, wherein each of the line segments has one or two free ends which are not connected to other mask pattern elements is to be transferred to a layer of resist. A first mask is formed by adding line extensions to each of the free ends of the line segments. A cutting mask is formed comprising rectangles enclosing each of the line extensions wherein one of the sides of said rectangles is coincident with the corresponding free end of said line segment. The first mask has opaque regions corresponding to the extended line segments. The cutting mask has transparent regions corresponding to the cutting pattern. In another embodiment a pattern having pattern openings comprising a number of line segments. In this embodiment the cutting pattern comprises rectangles having the same width as said line segments and add length to the line segments.

Abstract translation: 描述了两个掩模的掩模组和在双重曝光中使用这些掩模以避免由于光学邻近效应引起的线缩短的方法。 具有包括多个线段的图形元素的图案，其中每个线段具有未连接到其它掩模图案元件的一个或两个自由端将被转移到抗蚀剂层。 通过向线段的每个自由端添加线延伸来形成第一掩模。 形成切割掩模，其包括围绕每个线延伸的矩形，其中所述矩形的一个侧面与所述线段的对应的自由端重合。 第一掩模具有对应于延伸线段的不透明区域。 切割掩模具有对应于切割图案的透明区域。 在另一个实施例中，具有包括多个线段的图案开口的图案。 在该实施例中，切割图案包括具有与所述线段相同宽度的矩形，并且对线段增加长度。

公开(公告)号：US6165693A

公开(公告)日：2000-12-26

申请号：US135434

申请日：1998-08-17

Applicant: Chin-Lung Lin ,  Yao-Ching Ku

Inventor： Chin-Lung Lin ,  Yao-Ching Ku

IPC: G03F1/00 ,  G03C5/00

CPC classification number: G03F1/36

Abstract: For a dense-line mask pattern, if the ratio of space width to line width is larger than 2.0 and the size of the line width is less than the exposure wave length, or for an iso-line mask pattern, if the size of the line width is less than the exposure wave length, assist features should be added and OAI should be used to increase the process window. For a dense-line mask pattern, if the ratio of space width to line width is smaller than 2.0, or for an iso-line mask pattern, if the size of the line width is larger than the exposure wavelength, no assist feature should be added.

Abstract translation: 对于密集线掩模图案，如果空间宽度与线宽的比率大于2.0，并且线宽的尺寸小于曝光波长，或者对于等线掩模图案，如果尺寸 线宽小于曝光波长，应添加辅助功能，并应使用OAI增加工艺窗口。 对于密集线掩模图案，如果空间宽度与线宽的比率小于2.0，或者对于等线掩模图案，如果线宽的大小大于曝光波长，则不应该有辅助特征 添加。