公开(公告)号：US20120256276A1

公开(公告)日：2012-10-11

申请号：US13082387

申请日：2011-04-07

Applicant: Guang-Yaw Hwang ,  Chun-Hsien Lin ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Zhi-Cheng Lee ,  Shao-Hua Hsu ,  Yi-Wen Chen ,  Cheng-Guo Chen ,  Jung-Tsung Tseng ,  Chien-Ting Lin ,  Tong-Jyun Huang ,  Jie-Ning Yang ,  Tsung-Lung Tsai ,  Po-Jui Liao ,  Chien-Ming Lai ,  Ying-Tsung Chen ,  Cheng-Yu Ma ,  Wen-Han Hung ,  Che-Hua Hsu

Inventor： Guang-Yaw Hwang ,  Chun-Hsien Lin ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Zhi-Cheng Lee ,  Shao-Hua Hsu ,  Yi-Wen Chen ,  Cheng-Guo Chen ,  Jung-Tsung Tseng ,  Chien-Ting Lin ,  Tong-Jyun Huang ,  Jie-Ning Yang ,  Tsung-Lung Tsai ,  Po-Jui Liao ,  Chien-Ming Lai ,  Ying-Tsung Chen ,  Cheng-Yu Ma ,  Wen-Han Hung ,  Che-Hua Hsu

IPC: H01L29/78 ,  H01L21/3205

CPC classification number: H01L29/517 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846

Abstract: A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An O2 ambience treatment is performed on at least one layer of the multi-layered stack structure. A conductive layer is formed on the multi-layered stack structure.

Abstract translation: 提供一种制造金属栅极的方法。 该方法包括提供基板。 然后，在基板上形成栅极电介质层。 在栅极电介质层上形成具有功函数金属层的多层堆叠结构。 在多层堆叠结构的至少一层上进行O2气氛处理。 在多层堆叠结构上形成导电层。

公开(公告)号：US20120244669A1

公开(公告)日：2012-09-27

申请号：US13053223

申请日：2011-03-22

Applicant: Po-Jui Liao ,  Tsung-Lung Tsai ,  Chien-Ting Lin ,  Shao-Hua Hsu ,  Yi-Wei Chen ,  Hsin-Fu Huang ,  Tzung-Ying Lee ,  Min-Chuan Tsai ,  Chan-Lon Yang ,  Chun-Yuan Wu ,  Teng-Chun Tsai ,  Guang-Yaw Hwang ,  Chia-Lin Hsu ,  Jie-Ning Yang ,  Cheng-Guo Chen ,  Jung-Tsung Tseng ,  Zhi-Cheng Lee ,  Hung-Ling Shih ,  Po-Cheng Huang ,  Yi-Wen Chen ,  Che-Hua Hsu

Inventor： Po-Jui Liao ,  Tsung-Lung Tsai ,  Chien-Ting Lin ,  Shao-Hua Hsu ,  Yi-Wei Chen ,  Hsin-Fu Huang ,  Tzung-Ying Lee ,  Min-Chuan Tsai ,  Chan-Lon Yang ,  Chun-Yuan Wu ,  Teng-Chun Tsai ,  Guang-Yaw Hwang ,  Chia-Lin Hsu ,  Jie-Ning Yang ,  Cheng-Guo Chen ,  Jung-Tsung Tseng ,  Zhi-Cheng Lee ,  Hung-Ling Shih ,  Po-Cheng Huang ,  Yi-Wen Chen ,  Che-Hua Hsu

IPC: H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/823807 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7833

Abstract: The present invention provides a method of manufacturing semiconductor device having metal gates. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench. Then, a first metal layer is formed in the first trench. The second sacrifice gate is removed to form a second trench. Next, a second metal layer is formed in the first trench and the second trench. Lastly, a third metal layer is formed on the second metal layer wherein the third metal layer is filled into the first trench and the second trench.

Abstract translation: 本发明提供一种制造具有金属栅极的半导体器件的方法。 首先，提供基板。 具有第一牺牲栅极的第一导电型晶体管和具有第二牺牲栅极的第二导电型晶体管设置在衬底上。 去除第一牺牲栅极以形成第一沟槽。 然后，在第一沟槽中形成第一金属层。 去除第二牺牲栅极以形成第二沟槽。 接下来，在第一沟槽和第二沟槽中形成第二金属层。 最后，在第二金属层上形成第三金属层，其中第三金属层被填充到第一沟槽和第二沟槽中。

公开(公告)号：US08193050B2

公开(公告)日：2012-06-05

申请号：US12907016

申请日：2010-10-18

Applicant: Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

Inventor： Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

IPC: H01L21/8238

CPC classification number: H01L27/11

Abstract: A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening.

Abstract translation: 公开了一种制造半导体结构的方法。 提供具有第一晶体管的衬底，其具有第一虚拟栅极和具有第二虚拟栅极的第二晶体管。 第一晶体管和第二晶体管的导电类型不同。 同时去除第一和第二伪栅极以形成相应的第一和第二开口。 在基板上形成高k电介质层，第二导电层和第一低电阻导电层，并填充第一和第二开口，第一低电阻导电层填充第二开口。 第一开口中的第一低电阻导电层和第二导电层被去除。 然后在第一开口中形成第一导电层和第二低电阻导电层，第二低电阻导电层填充第一开口。

公开(公告)号：US20120134416A1

公开(公告)日：2012-05-31

申请号：US13206891

申请日：2011-08-10

Applicant: Jian-Liang Lin ,  Yu-Pao Tsai ,  Yi-Wen Chen ,  Yu-Wen Huang ,  Shaw-Min Lei

Inventor： Jian-Liang Lin ,  Yu-Pao Tsai ,  Yi-Wen Chen ,  Yu-Wen Huang ,  Shaw-Min Lei

IPC: H04N7/26

CPC classification number: H04N19/52

Abstract: A method and apparatus for deriving a temporal motion vector predictor (MVP) are disclosed. The MVP is derived for a current block of a current picture in Inter, or Merge, or Skip mode based on co-located reference blocks of a co-located block. The co-located reference blocks comprise an above-left reference block of the bottom-right neighboring block of the co-located block. The reference motion vectors associated with the co-located reference blocks are received and used to derive the temporal MVP. Various configurations of co-located reference blocks can be used to practice the present invention. If the MVP cannot be found based on the above-left reference block, search for the MVP can be continued based on other co-located reference blocks. When an MVP is found, the MVP is checked against the previously found MVP. If the MVP is the same as the previously found MVP, the search for MVP continues.

Abstract translation: 公开了用于导出时间运动矢量预测器（MVP）的方法和装置。 基于同位置块的同位置参考块，针对Inter或当前图像的当前块导出MVP，或合并或跳跃模式。 共同定位的参考块包括同位置块的右下相邻块的左上参考块。 与同位置参考块相关联的参考运动矢量被接收并用于导出时间MVP。 可以使用共同定位的参考块的各种配置来实施本发明。 如果基于上述左参考块不能找到MVP，则可以基于其他同位置参考块继续搜索MVP。 当找到MVP时，将针对先前发现的MVP检查MVP。 如果MVP与以前发现的MVP相同，则继续搜索MVP。

公开(公告)号：US20110251082A1

公开(公告)日：2011-10-13

申请号：US12756927

申请日：2010-04-08

Applicant: Hong-Lin Chan ,  Hsiu-Chuan Chou ,  Tzu-Chia Lai ,  Yi-Wen Chen ,  Ping-Chiang Lyu ,  Tian -Ren Lee ,  Hsin-Tsu Chan ,  Hsin-Hsin Shen ,  Wei-Ta Lee ,  Szu-Ting Lin ,  Ying-Chieh Lu ,  Chieh-Lin Wu

Inventor： Hong-Lin Chan ,  Hsiu-Chuan Chou ,  Tzu-Chia Lai ,  Yi-Wen Chen ,  Ping-Chiang Lyu ,  Tian -Ren Lee ,  Hsin-Tsu Chan ,  Hsin-Hsin Shen ,  Wei-Ta Lee ,  Szu-Ting Lin ,  Ying-Chieh Lu ,  Chieh-Lin Wu

IPC: C40B30/04 ,  C40B30/00 ,  C40B40/10

CPC classification number: G01N33/57415 ,  G01N2800/50 ,  G01N2800/52 ,  G01N2800/56

Abstract: The present invention uses 2-dimensional differential gel electrophoresisgel (2D-DIGE) and mass spetrum techniques to identify breast cancer biomarkers in transformed breast cells. In summary, the present invention identifies numerous putative breast cancer markers from various stages of breast cancer. The results of the invention aids in developing proteins identified as useful diagnostic and therapeutic candidates on breast cancer research.

Abstract translation: 本发明使用二维差示凝胶电泳凝胶（2D-DIGE）和大量的突出技术来鉴定转化的乳腺细胞中的乳腺癌生物标志物。 总之，本发明从乳腺癌的各个阶段鉴定出许多推定的乳腺癌标志物。 本发明的结果有助于开发鉴定为乳腺癌研究中有用的诊断和治疗候选物的蛋白质。

公开(公告)号：US20110034019A1

公开(公告)日：2011-02-10

申请号：US12907016

申请日：2010-10-18

Applicant: Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

Inventor： Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

IPC: H01L21/28

CPC classification number: H01L27/11

Abstract: A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening.

Abstract translation: 公开了一种制造半导体结构的方法。 提供具有第一晶体管的衬底，其具有第一虚拟栅极和具有第二虚拟栅极的第二晶体管。 第一晶体管和第二晶体管的导电类型不同。 同时去除第一和第二伪栅极以形成相应的第一和第二开口。 在基板上形成高k电介质层，第二导电层和第一低电阻导电层，并填充第一和第二开口，第一低电阻导电层填充第二开口。 第一开口中的第一低电阻导电层和第二导电层被去除。 然后在第一开口中形成第一导电层和第二低电阻导电层，第二低电阻导电层填充第一开口。

公开(公告)号：US20110031558A1

公开(公告)日：2011-02-10

申请号：US12907036

申请日：2010-10-19

Applicant: Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

Inventor： Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

IPC: H01L27/11

CPC classification number: H01L27/11

Abstract: A gate structure of a semiconductor device includes a first low resistance conductive layer, a second low resistance conductive layer, and a first type conductive layer disposed between and directly contacting sidewalls of the first low resistance conductive layer and the second low resistance conductive layer.

Abstract translation: 半导体器件的栅极结构包括第一低电阻导电层，第二低电阻导电层和设置在第一低电阻导电层和第二低电阻导电层的侧壁之间且直接接触的第一类型导电层。

公开(公告)号：US07838946B2

公开(公告)日：2010-11-23

申请号：US12058208

申请日：2008-03-28

Applicant: Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

Inventor： Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

IPC: H01L29/76

CPC classification number: H01L27/11

Abstract: A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening.

Abstract translation: 公开了一种制造半导体结构的方法。 提供具有第一晶体管的衬底，其具有第一虚拟栅极和具有第二虚拟栅极的第二晶体管。 第一晶体管和第二晶体管的导电类型不同。 同时去除第一和第二伪栅极以形成相应的第一和第二开口。 在基板上形成高k电介质层，第二导电层和第一低电阻导电层，并填充第一和第二开口，第一低电阻导电层填充第二开口。 第一开口中的第一低电阻导电层和第二导电层被去除。 然后在第一开口中形成第一导电层和第二低电阻导电层，第二低电阻导电层填满第一开口。

公开(公告)号：US20100213496A1

公开(公告)日：2010-08-26

申请号：US12703795

申请日：2010-02-11

Applicant: Yi-Wen Chen

Inventor： Yi-Wen Chen

IPC: H01L33/00

CPC classification number: H01L25/167 ,  H01L23/60 ,  H01L33/483 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49107 ,  H01L2924/12032 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A light emitting diode (LED) package including a carrier, a housing, at least one LED chip and at least one electrostatic discharge protector (ESD protector) is provided. The housing encapsulating a portion of the carrier has at least one first opening, at least one second opening and a barricade. The barricade separates the first opening from the second opening. The first opening and the second opening expose a first surface of the carrier. The LED chip is disposed on the first surface of the carrier, located in the first opening, and electrically connected to the carrier. The ESD protector is disposed on the first surface of the carrier, located in the second opening, and electrically connected to the carrier.

Abstract translation: 提供了包括载体，壳体，至少一个LED芯片和至少一个静电放电保护器（ESD保护器）的发光二极管（LED）封装。 封装载体的一部分的壳体具有至少一个第一开口，至少一个第二开口和路障。 路障将第一个开口与第二个开口分开。 第一开口和第二开口暴露载体的第一表面。 LED芯片设置在载体的第一表面上，位于第一开口中，并与载体电连接。 ESD保护器设置在载体的位于第二开口中的第一表面上，并电连接至载体。

公开(公告)号：US20090196452A1

公开(公告)日：2009-08-06

申请号：US12356574

申请日：2009-01-21

Applicant: Nengbin Wan ,  Bo Zhang ,  Yi-Wen Chen ,  Ming Zhang

Inventor： Nengbin Wan ,  Bo Zhang ,  Yi-Wen Chen ,  Ming Zhang

IPC: H04R11/04 ,  B32B37/12

CPC classification number: H04R9/08 ,  B60R25/04 ,  B60R25/2018 ,  B60R25/209 ,  H04R2410/07

Abstract: A microphone assembly includes a flexible holder, a microphone, and a piece of non-woven fabric. The flexible holder has a top opening. The microphone is fitted into the flexible holder. The piece of non-woven fabric is attached to the microphone and totally disposed in the top opening of the flexible holder.

Abstract translation: 麦克风组件包括柔性保持器，麦克风和一件无纺织物。 柔性保持器具有顶部开口。 麦克风安装在柔性支架上。 该无纺织物附着在麦克风上，并且完全设置在柔性保持器的顶部开口中。