公开(公告)号：US08080831B2

公开(公告)日：2011-12-20

申请号：US12784560

申请日：2010-05-21

申请人： Fumitaka Nakayama ,  Masatoshi Morikawa ,  Yutaka Hoshino ,  Tetsuo Uchiyama

发明人： Fumitaka Nakayama ,  Masatoshi Morikawa ,  Yutaka Hoshino ,  Tetsuo Uchiyama

IPC分类号： H01L21/02

CPC分类号： H01L21/823814 ,  H01L21/26586 ,  H01L23/3677 ,  H01L23/5223 ,  H01L23/5227 ,  H01L27/0617 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/0922 ,  H01L28/20 ,  H01L28/40 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/66659 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2924/13091 ,  H01L2924/30107 ,  H03F3/193 ,  H01L2924/00

摘要： A semiconductor device including a MISFET formed in a well at a main surface of a substrate, a second MISFET formed at a main surface of the substrate, and a passive element formed over the main surface of the substrate and having two terminals. A conductive film is formed at a rear face of the semiconductor substrate. The conductive film is connected with a fixed potential and also electrically connected with the conductive film.

摘要翻译： 一种半导体器件，包括形成在基板的主表面的阱中的MISFET，形成在基板的主表面处的第二MISFET以及形成在基板的主表面上并具有两个端子的无源元件。 导电膜形成在半导体衬底的背面。 导电膜与固定电位连接，并与导电膜电连接。

公开(公告)号：US20100097157A1

公开(公告)日：2010-04-22

申请号：US12644971

申请日：2009-12-22

申请人： Fumitaka NAKAYAMA ,  Masatoshi MORIKAWA ,  Yutaka HOSHINO ,  Tetsuo UCHIYAMA

发明人： Fumitaka NAKAYAMA ,  Masatoshi MORIKAWA ,  Yutaka HOSHINO ,  Tetsuo UCHIYAMA

IPC分类号： H03H7/38 ,  H01L27/06 ,  H03H2/00

CPC分类号： H01L21/823814 ,  H01L21/26586 ,  H01L23/3677 ,  H01L23/5223 ,  H01L23/5227 ,  H01L27/0617 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/0922 ,  H01L28/20 ,  H01L28/40 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/66659 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2924/13091 ,  H01L2924/30107 ,  H03F3/193 ,  H01L2924/00

摘要： A semiconductor device including a MISFET formed in a well at a main surface of a substrate, a second MISFET formed at a main surface of the substrate, and a passive element formed over the main surface of the substrate and having two terminals. A conductive film is formed at a rear face of the semiconductor substrate. The conductive film is connected with a fixed potential and also electrically connected with the conductive film.

摘要翻译： 一种半导体器件，包括形成在基板的主表面的阱中的MISFET，形成在基板的主表面处的第二MISFET以及形成在基板的主表面上并具有两个端子的无源元件。 导电膜形成在半导体衬底的背面。 导电膜与固定电位连接，并与导电膜电连接。

公开(公告)号：US20090108371A1

公开(公告)日：2009-04-30

申请号：US12341330

申请日：2008-12-22

申请人： Fumitaka NAKAYAMA ,  Masatoshi Morikawa ,  Yutaka Hoshino ,  Tetsuo Uchiyama

发明人： Fumitaka NAKAYAMA ,  Masatoshi Morikawa ,  Yutaka Hoshino ,  Tetsuo Uchiyama

IPC分类号： H01L27/06 ,  H01L29/86

CPC分类号： H01L21/823814 ,  H01L21/26586 ,  H01L23/3677 ,  H01L23/5223 ,  H01L23/5227 ,  H01L27/0617 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/0922 ,  H01L28/20 ,  H01L28/40 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/66659 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2924/13091 ,  H01L2924/30107 ,  H03F3/193 ,  H01L2924/00

摘要： A semiconductor device including a MISFET formed in a well at a main surface of a substrate, a second MISFET formed at a main surface of the substrate, and a passive element formed over the main surface of the substrate and having two terminals. A conductive film is formed at a rear face of the semiconductor substrate. The conductive film is connected with a fixed potential and also electrically connected with the conductive film.

摘要翻译： 一种半导体器件，包括形成在基板的主表面的阱中的MISFET，形成在基板的主表面处的第二MISFET以及形成在基板的主表面上并具有两个端子的无源元件。 导电膜形成在半导体衬底的背面。 导电膜与固定电位连接，并与导电膜电连接。

公开(公告)号：US20080061381A1

公开(公告)日：2008-03-13

申请号：US11926321

申请日：2007-10-29

申请人： Naotaka Hashimoto ,  Yutaka Hoshino ,  Shuji Ikeda

发明人： Naotaka Hashimoto ,  Yutaka Hoshino ,  Shuji Ikeda

IPC分类号： H01L27/108 ,  H01L21/8244

CPC分类号： H01L27/11 ,  G11C11/4125 ,  H01L23/5222 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1112 ,  H01L2924/0002 ,  Y10S257/903 ,  H01L2924/00

摘要： In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.

摘要翻译： 在具有由衬底上形成的六个MISFET构成的存储单元的完整CMOS SRAM中，具有堆叠结构的电容器元件由覆盖存储单元的下电极，上电极和插入了电容器绝缘膜（电介质膜）的电极形成 在下电极和上电极之间。 电容器元件的一个电极（下电极）连接到触发器电路的一个存储节点，另一个电极（上电极）连接到另一个存储节点。 结果，SRAM的存储单元的存储节点电容增加，以提高软错误电阻。

公开(公告)号：US20060261442A1

公开(公告)日：2006-11-23

申请号：US11493829

申请日：2006-07-27

申请人： Fumitaka Nakayama ,  Masatoshi Morikawa ,  Yutaka Hoshino ,  Tetsuo Uchiyama

发明人： Fumitaka Nakayama ,  Masatoshi Morikawa ,  Yutaka Hoshino ,  Tetsuo Uchiyama

IPC分类号： H01L29/00

CPC分类号： H01L21/823814 ,  H01L21/26586 ,  H01L23/3677 ,  H01L23/5223 ,  H01L23/5227 ,  H01L27/0617 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/0922 ,  H01L28/20 ,  H01L28/40 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/66659 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2924/13091 ,  H01L2924/30107 ,  H03F3/193 ,  H01L2924/00

摘要： A semiconductor device includes a transmission power amplifier having cascaded MOSFET amplification stages disposed over a main surface of a semiconductor substrate. A CMOSFET control circuit controls the amplification stages. A first capacitor is also provided having upper and lower metal film electrodes formed over the main surface of the semiconductor substrate. The amplification stages are electrically coupled to one another via an inter-stage matching circuit which includes the first capacitor.

摘要翻译： 半导体器件包括具有设置在半导体衬底的主表面上的级联MOSFET放大级的发射功率放大器。 CMOSFET控制电路控制放大级。 还提供了第一电容器，其具有形成在半导体衬底的主表面上的上金属膜电极和下金属膜电极。 放大级通过包括第一电容器的级间匹配电路彼此电耦合。

公开(公告)号：US07030449B2

公开(公告)日：2006-04-18

申请号：US10951940

申请日：2004-09-29

申请人： Naotaka Hashimoto ,  Yutaka Hoshino ,  Shuji Ikeda

发明人： Naotaka Hashimoto ,  Yutaka Hoshino ,  Shuji Ikeda

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/11 ,  G11C11/4125 ,  H01L23/5222 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1112 ,  H01L2924/0002 ,  Y10S257/903 ,  H01L2924/00

摘要： In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.

公开(公告)号：US20050042827A1

公开(公告)日：2005-02-24

申请号：US10951940

申请日：2004-09-29

申请人： Naotaka Hashimoto ,  Yutaka Hoshino ,  Shuji Ikeda

发明人： Naotaka Hashimoto ,  Yutaka Hoshino ,  Shuji Ikeda

IPC分类号： G11C11/412 ,  H01L21/8244 ,  H01L23/522 ,  H01L27/10 ,  H01L27/11 ,  H01L21/336

CPC分类号： H01L27/11 ,  G11C11/4125 ,  H01L23/5222 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1112 ,  H01L2924/0002 ,  Y10S257/903 ,  H01L2924/00

摘要： In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.

摘要翻译： 在具有由衬底上形成的六个MISFET构成的存储单元的完整CMOS SRAM中，具有堆叠结构的电容器元件由覆盖存储单元的下电极，上电极和插入了电容器绝缘膜（电介质膜）的电极形成 在下电极和上电极之间。 电容器元件的一个电极（下电极）连接到触发器电路的一个存储节点，另一个电极（上电极）连接到另一个存储节点。 结果，SRAM的存储单元的存储节点电容增加，以提高软错误电阻。

公开(公告)号：US06396111B2

公开(公告)日：2002-05-28

申请号：US09835419

申请日：2001-04-17

申请人： Naotaka Hashimoto ,  Yutaka Hoshino ,  Shuji Ikeda

发明人： Naotaka Hashimoto ,  Yutaka Hoshino ,  Shuji Ikeda

IPC分类号： H01L2976

CPC分类号： H01L27/11 ,  G11C11/4125 ,  H01L23/5222 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1112 ,  H01L2924/0002 ,  Y10S257/903 ,  H01L2924/00

摘要： In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.

公开(公告)号：US6030865A

公开(公告)日：2000-02-29

申请号：US66763

申请日：1998-04-28

申请人： Naotaka Hashimoto ,  Yutaka Hoshino ,  Shuji Ikeda

发明人： Naotaka Hashimoto ,  Yutaka Hoshino ,  Shuji Ikeda

IPC分类号： G11C11/412 ,  H01L21/8244 ,  H01L23/522 ,  H01L27/10 ,  H01L27/11

CPC分类号： H01L27/11 ,  G11C11/4125 ,  H01L23/5222 ,  H01L27/1104 ,  H01L27/1112 ,  H01L27/0207 ,  H01L2924/0002 ,  Y10S257/903

摘要： In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.

摘要翻译： 在具有由衬底上形成的六个MISFET构成的存储单元的完整CMOS SRAM中，具有堆叠结构的电容器元件由覆盖存储单元的下电极，上电极和插入了电容器绝缘膜（电介质膜）的电极形成 在下电极和上电极之间。 电容器元件的一个电极（下电极）连接到触发器电路的一个存储节点，另一个电极（上电极）连接到另一个存储节点。 结果，SRAM的存储单元的存储节点电容增加，以提高软错误电阻。

公开(公告)号：US08129784B2

公开(公告)日：2012-03-06

申请号：US12412128

申请日：2009-03-26

申请人： Makoto Hatori ,  Yutaka Hoshino

发明人： Makoto Hatori ,  Yutaka Hoshino

IPC分类号： H01L29/78

CPC分类号： H01L21/823468 ,  H01L21/823425 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/402 ,  H01L29/66659 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： The invention improves the performance of a semiconductor device. A metal silicide film is formed by a silicide process on a gate electrode and an n+-type source region of an LDMOSFET, and no such metal silicide film is formed on an n−-type offset drain region, an n-type offset drain region, and an n+-type drain region. A side wall spacer comprising a silicon film is formed via an insulating film on the side wall of the gate electrode over the drain side thereof, and a field plate electrode is formed by this side wall spacer. The field plate electrode does not extend above the gate electrode, and a metal silicide film is formed over the entire upper surface of the gate electrode in the silicide process.

摘要翻译： 本发明改进了半导体器件的性能。 金属硅化物膜通过硅化物工艺在LDMOSFET的栅电极和n +型源极区上形成，并且在n型偏移漏极区域，n型偏移漏极区域上不形成这种金属硅化物膜 ，和n +型漏极区域。 通过绝缘膜在其漏极侧的栅电极的侧壁上形成包括硅膜的侧壁隔片，并且通过该侧壁间隔物形成场板电极。 场板电极不在栅电极上方延伸，并且在硅化物工艺中在栅电极的整个上表面上形成金属硅化物膜。