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    System Control Using Sparse Data
    31.
    发明申请
    System Control Using Sparse Data 审中-公开

    公开(公告)号：US20200320013A1

    公开(公告)日：2020-10-08

    申请号：US16908182

    申请日：2020-06-22

    Applicant: Apple Inc.

    Inventor： Michael R. Seningen ,  Ben D. Jarrett ,  Edward M. McCombs ,  Greg M. Hess

    IPC: G06F12/10 ,  G06F12/06 ,  G11C11/419 ,  G06F17/16 ,  G11C7/10 ,  G11C5/14 ,  G11C8/06

    Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.

    Method and circuits for low latency initialization of static random access memory
    35.
    发明授权
    Method and circuits for low latency initialization of static random access memory 有权
    用于静态随机存取存储器低延迟初始化的方法和电路

    公开(公告)号：US09286971B1

    公开(公告)日：2016-03-15

    申请号：US14482613

    申请日：2014-09-10

    Applicant: Apple Inc.

    Inventor： Greg M. Hess ,  Ramesh Arvapalli ,  Andrew L. Arengo

    IPC: G11C11/00 ,  G11C7/00 ,  G11C8/00 ,  G11C11/419

    CPC classification number: G11C11/419 ,  G11C7/1078 ,  G11C7/20 ,  G11C8/10 ,  G11C8/12 ,  G11C11/413

    Abstract: A method and various circuit embodiments for low latency initialization of an SRAM are disclosed. In one embodiment, an IC includes an SRAM coupled to at least one functional circuit block. The SRAM includes a number of storage location arranged in rows and columns. The functional circuit block and the SRAM may be in different power domains. Upon initially powering up or a restoration of power, the functional circuit block may assert an initialization signal to begin an initialization process. Responsive to the initialization signal, level shifters may force assertion of various select/enable signals in a decoder associated with the SRAM. Thereafter, initialization data may be written to the SRAM. Writing initialization data may be performed on a row-by-row basis, with all columns in a row being written to substantially simultaneously.

    Abstract translation: 公开了用于SRAM的低延迟初始化的方法和各种电路实施例。 在一个实施例中，IC包括耦合到至少一个功能电路块的SRAM。 SRAM包括以行和列排列的多个存储位置。 功能电路块和SRAM可以在不同的电源域中。 在初始上电或恢复电源时，功能电路块可以断言初始化信号以开始初始化过程。 响应于初始化信号，电平移位器可以在与SRAM相关联的解码器中强制断言各种选择/使能信号。 此后，可以将初始化数据写入SRAM。 可以逐行地执行写入初始化数据，其中一行中的所有列被基本上同时写入。

    Dynamic global memory bit line usage as storage node
    36.
    发明授权
    Dynamic global memory bit line usage as storage node 有权
    动态全局内存位线用作存储节点

    公开(公告)号：US09236100B1

    公开(公告)日：2016-01-12

    申请号：US14497566

    申请日：2014-09-26

    Applicant: Apple Inc.

    Inventor： Greg M. Hess ,  Ramesh Arvapalli

    IPC: G11C7/10 ,  G11C7/12 ,  G11C7/22

    CPC classification number: G11C7/12 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1021 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/22 ,  G11C16/24 ,  G11C2207/2281

    Abstract: An apparatus, system, and method are contemplated in which the apparatus may include a memory with a plurality of pages, circuitry, and a plurality of pre-charge circuits. The circuitry may be configured to receive a first read command and address, corresponding to a given page. The plurality of pre-charge circuits may be configured to charge a plurality of data lines to a predetermined voltage. The circuitry may be configured to read data values from the memory, and transfer the data values to the plurality of data lines. The plurality of pre-charge circuits may be configured to maintain the data on the plurality of data lines. The circuitry may select a first subset of the maintained data, receive a second read command and a second address by the memory, and select a second subset of the maintained data responsive to a determination that the second address corresponds to the given page.

    Abstract translation: 设想一种装置，系统和方法，其中装置可以包括具有多页，电路和多个预充电电路的存储器。 电路可以被配置为接收对应于给定页面的第一读取命令和地址。 多个预充电电路可以被配置为将多条数据线充电到预定电压。 电路可以被配置为从存储器读取数据值，并将数据值传送到多条数据线。 多个预充电电路可以被配置为保持多个数据线上的数据。 电路可以选择维护的数据的第一子集，由存储器接收第二读取命令和第二地址，并且响应于第二地址对应于给定页面的确定来选择维护的数据的第二子集。

    CONFIGURABLE VOLTAGE REDUCTION FOR REGISTER FILE
    37.
    发明申请
    CONFIGURABLE VOLTAGE REDUCTION FOR REGISTER FILE 有权
    用于寄存器文件的可配置电压降低

    公开(公告)号：US20150348600A1

    公开(公告)日：2015-12-03

    申请号：US14291582

    申请日：2014-05-30

    Applicant: Apple Inc.

    Inventor： Ajay Kumar Bhatia ,  Anshul Y. Mehta ,  Amrinder S. Barn ,  Greg M. Hess

    IPC: G11C5/14 ,  G11C7/00

    CPC classification number: G11C5/147 ,  G11C29/021 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/4402

    Abstract: A system, a memory device and a method are contemplated in which the apparatus may include a plurality of memory cells, a plurality of voltage reduction circuits, and control circuitry. The plurality of voltage reduction circuits may be configured to reduce a voltage level of a power supply coupled to the plurality of memory cells. The control circuitry may be configured to select one of the voltage reduction circuits based on one or more operating parameters. The control circuitry may be further configured to activate the selected voltage reduction circuit upon receiving a write command directed towards the memory cells. The control circuitry may be further configured to execute the write command. Upon completion of the write command, the control circuitry may be further configured to de-activate the selected one of the voltage reduction circuits.

    Abstract translation: 可以想到一种系统，存储器件和方法，其中该装置可以包括多个存储器单元，多个电压降低电路和控制电路。 多个电压降低电路可以被配置为降低耦合到多个存储器单元的电源的电压电平。 控制电路可以被配置为基于一个或多个操作参数来选择一个电压降低电路。 控制电路还可以被配置为在接收到针对存储器单元的写入命令时激活所选择的电压降低电路。 控制电路还可以被配置为执行写命令。 在完成写入命令之后，控制电路还可以被配置为去激活所选择的一个电压降低电路。

    Low Voltage Register File Cell Structure
    38.
    发明申请
    Low Voltage Register File Cell Structure 审中-公开
    低电压寄存器文件单元结构

    公开(公告)号：US20140112429A1

    公开(公告)日：2014-04-24

    申请号：US13658115

    申请日：2012-10-23

    Applicant: APPLE INC.

    Inventor： Ajay Bhatia ,  Greg M. Hess ,  Sanjay P. Zambare

    IPC: G11C19/28

    CPC classification number: G11C19/28 ,  G11C11/412 ,  G11C2207/007

    Abstract: A register file cell structure to enable lower voltage writes is disclosed. In one embodiment, a register file includes a state element made up of two cross-coupled inverters. Each of the inverters includes a p-channel metal oxide semiconductor (PMOS) transistor having a source terminal coupled to a virtual voltage node. One or more PMOS transistors are coupled in series between the virtual voltage node and a global voltage node. Each of the one or more PMOS transistors includes a gate terminal that is hardwired to a ground node, and thus these devices remain active when power is applied to the global voltage node. The presence of the one or more PMOS devices coupled between the virtual and global voltage nodes results in the ability to overwrite contents stored in the state element at lower voltages than otherwise attainable without the one or more PMOS devices.

    Abstract translation: 公开了一种用于实现较低电压写入的寄存器文件单元结构。 在一个实施例中，寄存器文件包括由两个交叉耦合的反相器组成的状态元件。 每个反相器包括具有耦合到虚拟电压节点的源极端子的p沟道金属氧化物半导体（PMOS）晶体管。 一个或多个PMOS晶体管串联耦合在虚拟电压节点和全局电压节点之间。 一个或多个PMOS晶体管中的每一个包括硬接线到接地节点的栅极端子，因此当向全局电压节点施加功率时，这些器件保持有效。 耦合在虚拟和全局电压节点之间的一个或多个PMOS器件的存在导致在没有一个或多个PMOS器件的情况下以比其它可获得的电压更低的电压来覆盖存储在状态元件中的内容的能力。

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