公开(公告)号：US12117320B2

公开(公告)日：2024-10-15

申请号：US17366459

申请日：2021-07-02

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Shane J. Keil ,  Manu Gulati ,  Jung Wook Cho ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Timothy J. Millet ,  Joshua P. de Cesare ,  Anand Dalal ,  Michael F. Culbert

IPC: G01D9/00 ,  A61G3/06 ,  B60P1/43 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  G06F13/16

CPC classification number: G01D9/00 ,  A61G3/061 ,  B60P1/433 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  G06F13/1689 ,  Y02D10/00 ,  Y02D30/50

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when a central processing unit (CPU) processor and a memory controller of the SOC are powered off. The component may include a sensor capture unit to capture audio samples from an audio detector circuit and write them to a memory of the component. A processor of the component may be configured to search the audio samples for a predetermined pattern during a time when the CPU processor and the memory controller are powered down. In some embodiments, based on the audio samples filling to a threshold level in the memory of the component and a lack of detection of the predetermined pattern, the component is configured to wake up the memory controller and a path to the memory controller in order to write the audio sample to a memory controlled by the memory controller.

公开(公告)号：US20240095194A1

公开(公告)日：2024-03-21

申请号：US18469905

申请日：2023-09-19

Applicant: Apple Inc.

Inventor： Shane J. Keil ,  Gregory S. Mathews ,  Lakshmi Narasimha Murthy Nukala

IPC: G06F13/16

CPC classification number: G06F13/1626 ,  G06F13/1678 ,  G06F13/1689

Abstract: A memory control circuit coupled to multiple memory ranks may receive read and write requests for a different ranks of the multiple memory ranks. The memory control may allocate write requests to different slots based on the write requests target memory rank, and may adjust the number of slots available for a given memory rank during a write turn to improve write efficiency. The memory control circuit may also determine a number of ranks switches within a read turn based on whether a particular quality-of-service requirement associated with the read requests is being satisfied.

公开(公告)号：US20240094917A1

公开(公告)日：2024-03-21

申请号：US18469730

申请日：2023-09-19

Applicant: Apple Inc.

Inventor： Shane J. Keil ,  Gregory S. Mathews ,  Rakesh L. Notani

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0613 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/023

Abstract: A memory control circuit coupled to multiple memory ranks may receive read and write requests for a different ranks of the multiple memory ranks. The memory control may allocate write requests to different slots based on the write requests target memory rank, and may adjust the number of slots available for a given memory rank during a write turn to improve write efficiency. The memory control circuit may also determine a number of ranks switches within a read turn based on whether a particular quality-of-service requirement associated with the read requests is being satisfied.

公开(公告)号：US20230063772A1

公开(公告)日：2023-03-02

申请号：US17655324

申请日：2022-03-17

Applicant: Apple Inc.

Inventor： Gregory S. Mathews ,  Shane J. Keil

IPC: G06F13/16 ,  G06F1/06

Abstract: Techniques for scheduling memory operations are disclosed in which alternate read/write commands within a multi-bank memory operation are delayed beyond a minimum timing parameter in order to increase memory data bus utilization. The remaining read/write commands are not delayed beyond the minimum timing parameter. Every other clock cycle (e.g., even clock cycles) within the memory operation is reserved for activate commands, while other commands such as sync and read/write are scheduled on the intervening clock cycles (e.g., odd clock cycles). For memory devices for which a sync command (which causes a clock of the memory data bus to start) is to precede a corresponding read/write command by a number of clock cycles that would place it in a cycle reserved for activate commands, a particular operation mode is disclosed in which the memory device internally delays a received sync command.

公开(公告)号：US10901617B2

公开(公告)日：2021-01-26

申请号：US16565386

申请日：2019-09-09

Applicant: Apple Inc.

Inventor： Gregory S. Mathews ,  Shane J. Keil ,  Sukalpa Biswas ,  Lakshmi Narasimha Murthy Nukala ,  Thejasvi Magudilu Vijavaraj

IPC: G06F12/00 ,  G06F3/06

Abstract: A memory controller circuit coupled to a memory circuit that includes multiple banks may receive multiple access requests including a particular access request to a particular bank of the plurality of banks. The particular access request is associated with a particular virtual channel of a plurality of virtual channels. The memory controller circuit may select a given access requests of the multiple access requests based on an arbitration category value associated with a virtual channel of the given access request and modify the arbitration category value in response to selecting the given access request.

公开(公告)号：US10817219B2

公开(公告)日：2020-10-27

申请号：US16129735

申请日：2018-09-12

Applicant: Apple Inc.

Inventor： Lakshmi Narasimha Murthy Nukala ,  Sukalpa Biswas ,  Thejasvi Magudilu Vijavaraj ,  Shane J. Keil ,  Gregory S. Mathews

IPC: G06F3/06 ,  G06F13/16 ,  G06F9/48 ,  G06F9/54

Abstract: A memory controller circuit coupled to multiple memory circuits may receive a read request for a particular one of the memory circuits and insert the read request into one of multiple linked lists that includes a linked list whose entries correspond to previously received read requests and are linked according to respective ages of the read requests. The memory controller circuit may schedule the read request using a head pointer of one of the multiple linked lists.

公开(公告)号：US20200301615A1

公开(公告)日：2020-09-24

申请号：US16896027

申请日：2020-06-08

Applicant: Apple Inc.

Inventor： Shane J. Keil ,  Gregory S. Mathews ,  Lakshmi Narasimha Murthy Nukala ,  Thejasvi Magudilu Vijayaraj ,  Kai Lun Hsiung ,  Yanzhe Liu ,  Sukalpa Biswas

IPC: G06F3/06

Abstract: An apparatus includes a memory circuit and a memory controller circuit. The memory controller circuit may include a write request queue. The memory controller circuit may be configured to receive a memory request to access the memory circuit and determine if the memory request includes a read request or a write request. A received read request may be scheduled for execution, while a received write request may be stored in the write request queue. The memory controller circuit may reorder scheduled memory requests based on achieving a specified memory access efficiency and based on a number of write requests stored in the write request queue.

公开(公告)号：US20200159463A1

公开(公告)日：2020-05-21

申请号：US16751975

申请日：2020-01-24

Applicant: Apple Inc.

Inventor： Gregory S. Mathews ,  Kai Lun Hsiung ,  Lakshmi Narasimha Murthy Nukala ,  Peter Fu ,  Rakesh L. Notani ,  Sukalpa Biswas ,  Thejasvi Magudilu Vijayaraj ,  Yanzhe Liu ,  Shane J. Keil

IPC: G06F3/06

Abstract: Techniques relating to arbitration in a memory controller are disclosed. In some embodiments, the memory controller is configured to transition between read turns and writes turn according to a turn schedule. In some embodiments, the memory controller also receives reports from circuitry requesting memory transactions and determines a current latency tolerance value based on the reports. In some embodiments, the memory controller is configured to switch from a write turn to a read turn prior to a scheduled switch based on the current latency tolerance meeting a threshold value.

公开(公告)号：US20200065028A1

公开(公告)日：2020-02-27

申请号：US16112624

申请日：2018-08-24

Applicant: Apple Inc.

Inventor： Shane J. Keil ,  Gregory S. Mathews ,  Lakshmi Narasimha Murthy Nukala ,  Thejasvi Magudilu Vijayaraj ,  Kai Lun Hsiung ,  Yanzhe Liu ,  Sukalpa Biswas

IPC: G06F3/06

Abstract: An embodiment of an apparatus includes a memory circuit and a memory controller circuit. The memory controller circuit may include a write request queue. The memory controller circuit may be configured to receive a memory request to access the memory circuit and determine if the memory request includes a read request or a write request. A received read request may be scheduled for execution, while a received write request may be stored in the write request queue. The memory controller circuit may reorder scheduled memory requests based on achieving a specified memory access efficiency and based on a number of write requests stored in the write request queue.

公开(公告)号：US20200050396A1

公开(公告)日：2020-02-13

申请号：US16058647

申请日：2018-08-08

Applicant: Apple Inc.

Inventor： Shane J. Keil

IPC: G06F3/06 ,  G06F13/16 ,  G11C7/22 ,  G11C7/10 ,  G11C11/406

Abstract: A memory system includes a memory circuit including a plurality of pages, including a particular page having a page activation time. The memory system also includes a memory controller circuit configured to receive a memory access request corresponding to data of the particular page. The memory controller circuit is also configured to transmit, in response to a determination that the particular page is inactive, an activation command to the memory circuit to activate the particular page, and to schedule a future transmission of an initial memory command for the particular page based on the page activation time.