-
公开(公告)号：US11133043B2
公开(公告)日：2021-09-28
申请号：US16783104
申请日：2020-02-05
Applicant: Arm Limited
Inventor： Andy Wangkun Chen , Yew Keong Chong , Sriram Thyagarajan
Abstract: According to one implementation of the present disclosure, an integrated circuit includes first and second word-line decoder circuitry; one or more core arrays, respective input/output (I/O) circuitry for each of the one or more core arrays, and control circuitry coupled to the first and second word-line decoder circuitries, the one or more core arrays, and the respective I/O circuitries. Also, one or more control signals, activated from one or more control signals generated in the control circuitry, may be configured to select corresponding one or more core arrays of the one or more core arrays.
-
32.发明授权公开(公告)号：US10796053B2
公开(公告)日：2020-10-06
申请号：US16140461
申请日：2018-09-24
Applicant: Arm Limited
Inventor： Paul de Dood , Marlin Wayne Frederick, Jr. , Jerry Chaoyuan Wang , Brian Tracy Cline , Xiaoqing Xu , Andy Wangkun Chen , Yew Keong Chong , Tom Shore , Sriram Thyagarajan , Gus Yeung , Daniel J. Albers , David William Granda
IPC: G06F17/50 , G06F30/39 , G06F30/30 , G06F30/398 , G06F30/392 , G06F30/394
Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimised during generation of the layout of the cell.
-
公开(公告)号：US20190007043A1
公开(公告)日：2019-01-03
申请号：US15636428
申请日：2017-06-28
Applicant: ARM Limited
Inventor： Andy Wangkun Chen , Yew Keong Chong , Yicong Li , Hsin-Yu Chen , Sriram Thyagarajan
Abstract: A method to generate a circuit instance to include a plurality of pMOSFET instances, where each pMOSFET instance has a source terminal instance connected to one or more supply rail instances. The circuit instance includes impedance element instances, where each impedance element instance is connected to a source terminal instance and a drain terminal instance of a corresponding pMOSFET instance. Depending upon a set of requirements, one or more of the impedance element instances are in a high impedance state or a low impedance state.
-
公开(公告)号：US10140399B2
公开(公告)日：2018-11-27
申请号：US15387373
申请日：2016-12-21
Applicant: ARM Limited
Inventor： Hongwei Zhu , Mouli Rajaram Chollangi , Hemant Joshi , Yew Keong Chong , Satinderjit Singh , Betsie Jacob , Neeraj Dogra , Sriram Thyagarajan
Abstract: Various implementations described herein are directed to a computing device. The computing device may include a mapper module that receives a user configuration input of a destination corner for building a destination corner database. The mapper module may include a decision making engine that decides fabrication parameters for building the destination corner database based on the verified user configuration input and memory compiler metadata. The computing device may include a builder module that performs a simulation of the destination corner based on the fabrication parameters, collects simulation results data associated with the simulation, and builds the destination corner database for the destination corner based on the simulation results data and source corner data. The computing device may include a memory compiler that accesses the destination corner database and generates memory instance structures and their electronic digital automation (EDA) views for the destination corner based on the destination corner database.
-
公开(公告)号：US09600179B2
公开(公告)日：2017-03-21
申请号：US14446668
申请日：2014-07-30
Applicant: ARM Limited
Inventor： Yew Keong Chong , Michael Alan Filippo , Gus Yeung , Andy Wangkun Chen , Sriram Thyagarajan
CPC classification number: G06F3/06 , G06F1/3275 , G11C7/00 , G11C7/08 , G11C7/22 , G11C8/08 , Y02D10/13 , Y02D10/14
Abstract: A memory device and a method of operating the memory device are provided. The memory device comprises a plurality of storage units and access control circuitry. The access control is configured to receive an access request and in response to the access request to initiate an access procedure in each of the plurality of storage units. The access control circuitry is configured to receive an access kill signal after the access procedure has been initiated and, in response to the access kill signal, to initiate an access suppression to suppress the access procedure in at least one of the plurality of storage units. Hence, by initiating the access procedures in all storage units in response to the access request, e.g. without waiting for a further indication of a specific storage unit in which to carry out the access procedure, the overall access time for the memory device kept low, but by enabling at least one of the access procedures later to be suppressed in response to the access kill signal dynamic power consumption of the memory device can be reduced.
-
Patent Agency Ranking
公开(公告)号：US20160034403A1
公开(公告)日：2016-02-04
申请号：US14446668
申请日：2014-07-30
Applicant: ARM Limited
Inventor： Yew Keong Chong , Michael Alan Filippo , Gus Yeung , Andy Wangkun Chen , Sriram Thyagarajan
IPC: G06F12/08
CPC classification number: G06F3/06 , G06F1/3275 , G11C7/00 , G11C7/08 , G11C7/22 , G11C8/08 , Y02D10/13 , Y02D10/14
Abstract: A memory device and a method of operating the memory device are provided. The memory device comprises a plurality of storage units and access control circuitry. The access control is configured to receive an access request and in response to the access request to initiate an access procedure in each of the plurality of storage units. The access control circuitry is configured to receive an access kill signal after the access procedure has been initiated and, in response to the access kill signal, to initiate an access suppression to suppress the access procedure in at least one of the plurality of storage units. Hence, by initiating the access procedures in all storage units in response to the access request, e.g. without waiting for a further indication of a specific storage unit in which to carry out the access procedure, the overall access time for the memory device kept low, but by enabling at least one of the access procedures later to be suppressed in response to the access kill signal dynamic power consumption of the memory device can be reduced.
Abstract translation: 提供了存储器件和操作存储器件的方法。 存储器件包括多个存储单元和访问控制电路。 访问控制被配置为接收访问请求并且响应于访问请求以在多个存储单元中的每一个中发起访问过程。 所述访问控制电路被配置为在所述访问过程已经被启动之后接收访问终止信号，并且响应于所述访问禁止信号来启动访问抑制以抑制所述多个存储单元中的至少一个中的访问过程。 因此，通过响应于访问请求在所有存储单元中启动访问过程，例如， 在不等待对其进行访问过程的特定存储单元的进一步指示的情况下，存储器件的总访问时间保持为低，但是通过使访问过程中的至少一个随后能够被响应于访问被抑制 杀死信号动态功耗的存储器件可以减少。
-
公开(公告)号：US20150049568A1
公开(公告)日：2015-02-19
申请号：US13967908
申请日：2013-08-15
Applicant: ARM Limited
Inventor： Sriram Thyagarajan , Yew Keong Chong , Wang-Kun Chen , Gus Yeung
IPC: G11C8/00
Abstract: A memory device comprises an array of bitcells arranged as a plurality of rows of bitcells and a plurality of columns of bitcells, and has a plurality of wordlines and a plurality of readout channels. A control unit is configured to control access to the array of bitcells, wherein in response to a memory access request specifying a memory address the control unit is configured to activate a selected wordline and to activate the plurality of readout channels, and to access a row of bitcells in said array storing a data word and addressed by the memory address. The data word consists of a number of data bits given by a number of bitcells in each row of bitcells. The control unit is further configured to be responsive to a masking signal and, when the masking signal is asserted when said memory access request is received, the control unit is configured to activate only a portion of the selected wordline and a portion of the plurality of readout channels, such that only a portion of the data word is accessed.
Abstract translation: 存储器件包括排列成多行比特单元和多列比特单元的位单元阵列，并且具有多个字线和多个读出通道。 控制单元被配置为控制对位单元阵列的访问，其中响应于指定存储器地址的存储器访问请求，控制单元被配置为激活所选择的字线并激活多个读出通道，并且访问行 所述阵列中的位单元存储数据字并由存储器地址寻址。 数据字由每行位单元中的多个位单元给出的多个数据位组成。 所述控制单元还被配置为响应于屏蔽信号，并且当接收到所述存储器访问请求时屏蔽信号被断言时，所述控制单元被配置为仅激活所选字线的一部分和所述多个 读出通道，使得仅访问数据字的一部分。
-
公开(公告)号：US08947968B2
公开(公告)日：2015-02-03
申请号：US13936512
申请日：2013-07-08
Applicant: ARM Limited
Inventor： Wang-Kun Chen , Yew Keong Chong , Sriram Thyagarajan , Gus Yeung
CPC classification number: G11C11/417 , G11C5/148
Abstract: A memory has a normal mode and a power saving mode. The memory has bitline precharge circuitry which during the normal mode selectively couples a pair of bitlines to a precharge node to charge the bitlines to a given voltage level. During the power saving mode the bitlines are isolated from the precharge node. Voltage control circuitry is provided to maintain the precharge node at a first voltage level during the normal mode and at a second voltage level less than the first voltage level during the power saving mode. By reducing the voltage level at the precharge node during the power saving mode, the amount of inrush current occurring when switching from power saving mode to normal mode can be reduced, and this enables the wakeup time to be reduced when returning from power saving mode to normal mode.
Abstract translation: 存储器具有正常模式和省电模式。 存储器具有位线预充电电路，其在正常模式期间选择性地将一对位线耦合到预充电节点，以将位线充电到给定的电压电平。 在省电模式期间，位线与预充电节点隔离。 提供电压控制电路以在正常模式期间将预充电节点保持在第一电压电平，并且在省电模式期间处于小于第一电压电平的第二电压电平。 通过在省电模式下减小预充电节点处的电压电平，可以减少从省电模式切换到正常模式时所产生的浪涌电流量，并且能够在从省电模式返回时减少唤醒时间 正常模式。
-
公开(公告)号：US12300310B2
公开(公告)日：2025-05-13
申请号：US17971226
申请日：2022-10-21
Applicant: Arm Limited
Inventor： Vianney Antoine Choserot , Andy Wangkun Chen , Yew Keong Chong , Sriram Thyagarajan
IPC: G11C11/41 , G11C11/412 , G11C11/418 , G11C11/419
Abstract: Various implementations described herein are related to a device having a storage node with a bitcell. The device may have a first stage that performs a first write based on an internal bitline signal, a first write wordline signal and a second write wordline signal. The first stage outputs the internal bitline signal. The device may have a second stage that receives the internal bitline signal and performs a second write of the internal bitline signal to the bitcell. The device may have a third stage with write wordline ports and write bitline ports. The third stage provides the internal bitline signal based on a selected write wordline signal from a write wordline port of the write wordline ports and based on a selected bitline signal based on a write bitline port of the write bitline ports.
-
公开(公告)号：US12164855B2
公开(公告)日：2024-12-10
申请号：US17209903
申请日：2021-03-23
Applicant: Arm Limited
Inventor： Sriram Thyagarajan , Yew Keong Chong , Sony , Andy Wangkun Chen
IPC: G06F30/3953
Abstract: Various implementations described herein are directed to a method for identifying pre-routed metal lines in a higher layer of a multi-layered structure. The method may recognize gaps in the pre-routed metal lines of the higher layer, and also, the method may automatically fill the gaps with conductive stubs to modify the pre-routed metal lines in the higher layer as a continuous metal line with an extended length.
-
-
-
-
-
-
-
-
-
Search Results
81
records
(took 0.017 seconds)
