公开(公告)号：US07575973B2

公开(公告)日：2009-08-18

申请号：US11691917

申请日：2007-03-27

申请人： Nima Mokhlesi ,  Roy Scheuerlein

发明人： Nima Mokhlesi ,  Roy Scheuerlein

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/0605 ,  H01L27/0688 ,  H01L27/11568 ,  H01L27/11582

摘要： A method of making a monolithic, three dimensional NAND string including a first memory cell located over a second memory cell, includes growing a semiconductor active region of second memory cell, and epitaxially growing a semiconductor active region of the first memory cell on the semiconductor active region of the second memory cell in a different growth step from the step of growing the semiconductor active region of second memory cell.

摘要翻译： 一种制造包括位于第二存储单元之上的第一存储单元的单片三维NAND串的方法包括：生长第二存储单元的半导体有源区，并且在半导体激活时外延生长第一存储单元的半导体有源区 与第二存储单元的半导体有源区的生长步骤不同的生长步骤中的第二存储单元的区域。

公开(公告)号：US20070069241A1

公开(公告)日：2007-03-29

申请号：US11173973

申请日：2005-07-01

申请人： Xiaoyu Yang ,  Roy Scheuerlein ,  Feng Li ,  Albert Meeks

发明人： Xiaoyu Yang ,  Roy Scheuerlein ,  Feng Li ,  Albert Meeks

IPC分类号： H01L27/10 ,  H01L21/82

CPC分类号： H01L45/12 ,  G11C17/00 ,  G11C17/16 ,  H01L23/5252 ,  H01L27/101 ,  H01L45/04 ,  H01L45/146 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory array having memory cells comprising a diode and an antifuse can be made smaller and programmed at lower voltage by using antifuse materials having higher dielectric constant and higher acceleration factor than silicon dioxide, and by using diodes having lower band gaps than silicon. Such memory arrays can be made to have long operating lifetimes by using the high acceleration factor and lower band gap materials. Antifuse materials having dielectric constants between 5 and 27, for example hafnium silicon oxynitride or hafnium silicon oxide are particularly effective. Diode materials with band gaps lower than silicon, such as germanium or a silicon-germanium alloy are particularly effective.

摘要翻译： 通过使用具有比二氧化硅更高的介电常数和更高的加速因子的反熔丝材料，并且通过使用具有比硅更低的带隙的二极管，可以使具有包括二极管和反熔丝的存储单元的存储器阵列更小并且在较低的电压下编程。 这样的存储器阵列可以通过使用高加速因子和较低带隙材料而具有长的工作寿命。 具有介于5和27之间的介电常数的防腐材料，例如铪硅氮氧化物或氧化铪铪是特别有效的。 带隙低于硅的二极管材料，例如锗或硅 - 锗合金是特别有效的。

公开(公告)号：US20070008785A1

公开(公告)日：2007-01-11

申请号：US11179077

申请日：2005-07-11

申请人： Roy Scheuerlein

发明人： Roy Scheuerlein

IPC分类号： G11C7/10

CPC分类号： G11C13/0011 ,  G11C11/5614 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/71 ,  G11C2213/79

摘要： A non-volatile memory cell includes a switchable resistor memory element in series with a switch device. An array of such cells may be programmed using only positive voltages. A method for programming such cells also supports a direct write of both 0 and 1 data states without requirement of a block erase operation, and is scalable for use with relatively low voltage power supplies. A method for reading such cells reduces read disturb of a selected memory cell by impressing a read bias voltage having a polarity opposite that of a set voltage employed to change the switchable resistor memory element to a low resistance state. Such programming and read methods are well suited for use in a three-dimensional memory array formed on multiple levels above a substrate, particularly those having extremely compact array line drivers on very tight layout pitch.

摘要翻译： 非易失性存储单元包括与开关装置串联的可切换电阻存储元件。 可以仅使用正电压来编程这样的单元阵列。 用于编程这样的单元的方法还支持0和1数据状态的直接写入，而不需要块擦除操作，并且可扩展以用于相对低电压的电源。 用于读取这种单元的方法通过将具有极性与用于将可切换电阻器存储元件改变为低电阻状态的设定电压的极性相反的读取偏置电压来减小所选存储单元的读取干扰。 这种编程和读取方法非常适用于形成在衬底上的多个层上的三维存储器阵列，特别是在非常紧凑的布局间距上具有非常紧凑的阵列线驱动器的那些。

公开(公告)号：US20060285422A1

公开(公告)日：2006-12-21

申请号：US11157293

申请日：2005-06-20

申请人： Roy Scheuerlein

发明人： Roy Scheuerlein

IPC分类号： G11C8/00

CPC分类号： H01L27/1203 ,  G11C11/404 ,  H01L21/84 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/12 ,  H01L29/7841

摘要： A plurality of integrated circuit features are provided in the context of an array of memory cells including a plurality of word lines and a plurality of bit lines. Each memory cell includes a floating body or is volatile memory. The aforementioned features may include, among others, an option whereby the foregoing bit lines may be situated below a channel region of corresponding memory cells, etc.

公开(公告)号：US20060221758A1

公开(公告)日：2006-10-05

申请号：US11420787

申请日：2006-05-29

申请人： Christopher Petti ,  Roy Scheuerlein ,  Tanmay Kumar ,  Abhijit Bandyopadhyay

发明人： Christopher Petti ,  Roy Scheuerlein ,  Tanmay Kumar ,  Abhijit Bandyopadhyay

IPC分类号： G11C8/00

CPC分类号： G11C8/14 ,  G11C5/02 ,  G11C5/063 ,  G11C8/08 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/10894 ,  H01L27/10897

摘要： A multi-headed word line driver circuit incorporates bent-gate transistors to reduce the pitch otherwise achievable for interfacing to tightly-pitched array lines. In certain exemplary embodiments, a three-dimensional memory array includes multiple memory blocks and array lines traversing horizontally across at least one memory block. Vertical active area stripes are disposed beneath a first memory block, and a respective plurality of bent-gate electrodes intersects each respective active area stripe to define individual source/drain regions. Every other source/drain region is coupled to a bias node for the active area stripe, and remaining source/drain regions are respectively coupled to a respective array line associated with the first memory block, thereby forming a respective first driver transistor for the respective array line. In certain embodiments, a respective plurality of complementary array line driver circuits is disposed on each side of a connection area between adjacent memory blocks, and each such driver circuit is responsive to a single driver input node.

摘要翻译： 多头字线驱动电路包括弯栅晶体管，以减少为了与紧密排列的阵列线连接而实现的间距。 在某些示例性实施例中，三维存储器阵列包括穿过至少一个存储器块水平横越的多个存储器块和阵列线。 垂直有源区条纹设置在第一存储块下方，并且相应的多个弯曲栅电极与每个相应的有源区条纹相交以限定各个源/漏区。 每个其它源极/漏极区域耦合到用于有源区域条纹的偏置节点，并且剩余的源极/漏极区域分别耦合到与第一存储器模块相关联的相应阵列线，从而形成用于相应阵列的相应的第一驱动器晶体管 线。 在某些实施例中，相应的多个互补阵列线驱动器电路设置在相邻存储块之间的连接区域的每一侧上，并且每个这样的驱动器电路响应于单个驱动器输入节点。

公开(公告)号：US20060157679A1

公开(公告)日：2006-07-20

申请号：US11040262

申请日：2005-01-19

申请人： Roy Scheuerlein

发明人： Roy Scheuerlein

IPC分类号： H01L29/02

CPC分类号： G11C11/21 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481

摘要： A memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In order to avoid disturbing unselected memory cells during sequential writing, previously selected word and bit lines are brought to their unselected voltages before new bit lines and word lines are selected. A modified current mirror structure controls state switching of the phase change material.

公开(公告)号：US20050094445A1

公开(公告)日：2005-05-05

申请号：US10976598

申请日：2004-10-29

申请人： Yu Lu ,  William Reohr ,  Roy Scheuerlein

发明人： Yu Lu ,  William Reohr ,  Roy Scheuerlein

IPC分类号： G11C7/00 ,  G11C11/15 ,  G11C11/16

CPC分类号： G11C11/16

摘要： A magnetic random access memory circuit comprises a plurality of magnetic memory cells, each of the memory cells including a magnetic storage element having an easy axis and a hard axis associated therewith, and a plurality of column lines and row lines for selectively accessing one or more of the memory cells, each of the memory cells being proximate to an intersection of one of the column lines and one of the row lines. Each of the magnetic memory cells is arranged such that the easy axis is substantially parallel to a direction of flow of a sense current and the hard axis is substantially parallel to a direction of flow of a write current.

摘要翻译： 磁性随机存取存储器电路包括多个磁存储器单元，每个存储单元包括具有容易轴的磁存储元件和与其相关联的硬轴，以及多个列线和行线，用于选择性地访问一个或多个 的存储单元，每个存储器单元靠近一列列线和一行行的交点。 每个磁存储单元被布置成使得容易轴基本上平行于感测电流的流动方向，并且硬轴基本上平行于写入电流的流动方向。

公开(公告)号：US08547725B2

公开(公告)日：2013-10-01

申请号：US12703289

申请日：2010-02-10

申请人： Tanmay Kumar ,  Roy Scheuerlein ,  Pankaj Kalra ,  Jingyan Zhang

发明人： Tanmay Kumar ,  Roy Scheuerlein ,  Pankaj Kalra ,  Jingyan Zhang

IPC分类号： G11C11/00

CPC分类号： G11C11/56 ,  B82Y10/00 ,  G11C7/04 ,  G11C13/00 ,  G11C13/0069 ,  G11C13/025 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/19 ,  G11C2213/35 ,  G11C2213/72

摘要： A method of programming a nonvolatile memory cell. The nonvolatile memory cell includes a diode steering element in series with a carbon storage element The method includes providing a first voltage to the nonvolatile memory cell. The first voltage reverse biases the diode steering element. The carbon storage element sets to a lower resistivity state.

摘要翻译： 一种编程非易失性存储单元的方法。 非易失性存储单元包括与碳储存元件串联的二极管操作元件。该方法包括向非易失性存储单元提供第一电压。 第一电压反向偏置二极管转向元件。 碳储存元件设定为较低的电阻率状态。

公开(公告)号：US20120302029A1

公开(公告)日：2012-11-29

申请号：US13571100

申请日：2012-08-09

申请人： Andrei Mihnea ,  Deepak C. Sekar ,  George Samachisa ,  Roy Scheuerlein ,  Li Xiao

发明人： Andrei Mihnea ,  Deepak C. Sekar ,  George Samachisa ,  Roy Scheuerlein ,  Li Xiao

IPC分类号： H01L21/02

CPC分类号： G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/72 ,  H01L27/24

摘要： A storage system and method for forming a storage system that uses punch-through diodes as a steering element in series with a reversible resistivity-switching element is described. The punch-through diode allows bipolar operation of a cross-point memory array. The punch-through diode may have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. Therefore, it is compatible with bipolar switching in cross-point memory arrays having resistive switching elements. The punch-through diode may be a N+/P−/N+ device or a P+/N−/P+ device.

摘要翻译： 描述了一种用于形成使用穿通二极管作为与可逆电阻率切换元件串联的转向元件的存储系统的存储系统和方法。 穿通二极管允许交叉点存储器阵列的双极性操作。 穿通二极管可具有对称的非线性电流/电压关系。 穿通二极管在选择的电池的高偏压下具有高电流，对于未选择的电池，在低偏压下具有低泄漏电流。 因此，它与具有电阻式开关元件的交叉点存储器阵列中的双极开关兼容。 穿通二极管可以是N + / P- / N +器件或P + / N- / P +器件。

公开(公告)号：US20120236624A1

公开(公告)日：2012-09-20

申请号：US13051885

申请日：2011-03-18

申请人： Xiying Costa ,  Yibo Nian ,  Roy Scheuerlein ,  Tz-Yi Liu ,  Chandrasekhar Reddy Gorla

发明人： Xiying Costa ,  Yibo Nian ,  Roy Scheuerlein ,  Tz-Yi Liu ,  Chandrasekhar Reddy Gorla

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C11/56 ,  G11C11/5664 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0064 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2013/0076 ,  G11C2013/0092 ,  G11C2213/32

摘要： Improved methods for programming multi-level metal oxide memory cells balance applied voltage and current to provide improved performance. Set programming, which transitions the memory cell to a lower resistance state, is accomplished by determining an appropriate programming voltage and current limit for the objective resistance state to be achieved in the programming and then applying a pulse having the determined set electrical characteristics. Reset programming, which transitions the memory cell to a higher resistance state, is accomplished by determining an appropriate programming voltage and optionally current limit for the state to be achieved in the programming and then applying a pulse having the determined electrical characteristics. The algorithm used to determine the appropriate set or reset programming voltage and current values provides for effective programming without stressing the memory element. The electrical characteristics for programming pulses may be stored in a data table used in a table look up algorithm.

摘要翻译： 改进的多级金属氧化物存储单元的编程方法平衡施加的电压和电流，以提供更好的性能。 通过为编程中要实现的目标电阻状态确定适当的编程电压和电流限制，然后施加具有确定的设定电气特性的脉冲来实现将存储器单元转换到较低电阻状态的设置编程。 将存储器单元转换到较高电阻状态的复位编程通过确定编程中要实现的状态的适当编程电压和可选的电流限制，然后施加具有确定的电特性的脉冲来实现。 用于确定适当的设置或复位编程电压和电流值的算法提供有效的编程，而不会对存储元件造成影响。 编程脉冲的电气特性可以存储在表查找算法中使用的数据表中。