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    Method for using a multi-use memory cell and memory array
    2.
    发明申请
    Method for using a multi-use memory cell and memory array 有权
    使用多用途存储单元和存储器阵列的方法

    公开(公告)号：US20070070690A1

    公开(公告)日：2007-03-29

    申请号：US11496984

    申请日：2006-07-31

    申请人： Roy Scheuerlein ,  Tanmay Kumar

    发明人： Roy Scheuerlein ,  Tanmay Kumar

    IPC分类号： G11C11/14

    CPC分类号： G11C11/5692 ,  G11C11/005 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C17/14 ,  G11C2211/5641 ,  G11C2211/5646 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/76 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/148

    摘要： A method for using a multi-use memory cell and memory array are disclosed. In one preferred embodiment, a memory cell is operable as a one-time programmable memory cell or a rewritable memory cell. The memory cell comprises a memory element comprising a semiconductor material configurable to one of at least three resistivity states, wherein a first resistivity state is used to represent a data state of the memory cell when the memory cell operates as a one-time programmable memory cell but not when the memory cell operates as a rewritable memory cell. A memory array with such memory cells is also disclosed. In another preferred embodiment, a memory cell is provided comprising a switchable resistance material, wherein the memory cell is operable in a first mode in which the memory cell is programmed with a forward bias and a second mode in which the memory cell is programmed with a reverse bias.

    摘要翻译： 公开了一种使用多用存储单元和存储器阵列的方法。 在一个优选实施例中，存储器单元可操作为一次性可编程存储器单元或可重写存储单元。 存储单元包括存储元件，其包括可配置为至少三种电阻率状态之一的半导体材料，其中当存储器单元作为一次可编程存储单元操作时，第一电阻率状态用于表示存储单元的数据状态 但是当存储器单元作为可重写存储单元时不起作用。 还公开了具有这种存储单元的存储器阵列。 在另一个优选实施例中，提供了一种包括可切换电阻材料的存储单元，其中存储单元可在第一模式中操作，其中存储单元用正向偏置和第二模式编程，其中存储单元用 反向偏差。

    TRANSISTOR LAYOUT CONFIGURATION FOR TIGHT-PITCHED MEMORY ARRAY LINES
    3.
    发明申请
    TRANSISTOR LAYOUT CONFIGURATION FOR TIGHT-PITCHED MEMORY ARRAY LINES 有权
    用于紧凑的内存阵列的晶体管布局配置

    公开(公告)号：US20060221758A1

    公开(公告)日：2006-10-05

    申请号：US11420787

    申请日：2006-05-29

    申请人： Christopher Petti ,  Roy Scheuerlein ,  Tanmay Kumar ,  Abhijit Bandyopadhyay

    发明人： Christopher Petti ,  Roy Scheuerlein ,  Tanmay Kumar ,  Abhijit Bandyopadhyay

    IPC分类号： G11C8/00

    CPC分类号： G11C8/14 ,  G11C5/02 ,  G11C5/063 ,  G11C8/08 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/10894 ,  H01L27/10897

    摘要： A multi-headed word line driver circuit incorporates bent-gate transistors to reduce the pitch otherwise achievable for interfacing to tightly-pitched array lines. In certain exemplary embodiments, a three-dimensional memory array includes multiple memory blocks and array lines traversing horizontally across at least one memory block. Vertical active area stripes are disposed beneath a first memory block, and a respective plurality of bent-gate electrodes intersects each respective active area stripe to define individual source/drain regions. Every other source/drain region is coupled to a bias node for the active area stripe, and remaining source/drain regions are respectively coupled to a respective array line associated with the first memory block, thereby forming a respective first driver transistor for the respective array line. In certain embodiments, a respective plurality of complementary array line driver circuits is disposed on each side of a connection area between adjacent memory blocks, and each such driver circuit is responsive to a single driver input node.

    摘要翻译： 多头字线驱动电路包括弯栅晶体管，以减少为了与紧密排列的阵列线连接而实现的间距。 在某些示例性实施例中，三维存储器阵列包括穿过至少一个存储器块水平横越的多个存储器块和阵列线。 垂直有源区条纹设置在第一存储块下方，并且相应的多个弯曲栅电极与每个相应的有源区条纹相交以限定各个源/漏区。 每个其它源极/漏极区域耦合到用于有源区域条纹的偏置节点，并且剩余的源极/漏极区域分别耦合到与第一存储器模块相关联的相应阵列线，从而形成用于相应阵列的相应的第一驱动器晶体管 线。 在某些实施例中，相应的多个互补阵列线驱动器电路设置在相邻存储块之间的连接区域的每一侧上，并且每个这样的驱动器电路响应于单个驱动器输入节点。

    Multi-use memory cell and memory array
    4.
    发明申请
    Multi-use memory cell and memory array 审中-公开
    多用存储单元和存储器阵列

    公开(公告)号：US20070069276A1

    公开(公告)日：2007-03-29

    申请号：US11496985

    申请日：2006-07-31

    申请人： Roy Scheuerlein ,  Tanmay Kumar

    发明人： Roy Scheuerlein ,  Tanmay Kumar

    IPC分类号： H01L29/76

    CPC分类号： G11C11/5692 ,  G11C11/005 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C17/14 ,  G11C2211/5641 ,  G11C2211/5646 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/76 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/148

    摘要： A multi-use memory cell and memory array are disclosed. In one preferred embodiment, a memory cell is operable as a one-time programmable memory cell or a rewritable memory cell. The memory cell comprises a memory element comprising a semiconductor material configurable to one of at least three resistivity states, wherein a first resistivity state is used to represent a data state of the memory cell when the memory cell operates as a one-time programmable memory cell but not when the memory cell operates as a rewritable memory cell. A memory array with such memory cells is also disclosed. In another preferred embodiment, a memory cell is provided comprising a switchable resistance material, wherein the memory cell is operable in a first mode in which the memory cell is programmed with a forward bias and a second mode in which the memory cell is programmed with a reverse bias.

    摘要翻译： 公开了一种多用途存储器单元和存储器阵列。 在一个优选实施例中，存储器单元可操作为一次性可编程存储器单元或可重写存储单元。 存储单元包括存储元件，其包括可配置为至少三种电阻率状态之一的半导体材料，其中当存储器单元作为一次可编程存储单元操作时，第一电阻率状态用于表示存储单元的数据状态 但是当存储器单元作为可重写存储单元时不起作用。 还公开了具有这种存储单元的存储器阵列。 在另一个优选实施例中，提供了一种包括可切换电阻材料的存储单元，其中存储单元可在第一模式中操作，其中存储单元用正向偏置和第二模式编程，其中存储单元用 反向偏差。

    Method for using a memory cell comprising switchable semiconductor memory element with trimmable resistance
    5.
    发明申请
    Method for using a memory cell comprising switchable semiconductor memory element with trimmable resistance 有权
    一种用于使用具有可调整电阻的可切换半导体存储元件的存储单元的方法

    公开(公告)号：US20070072360A1

    公开(公告)日：2007-03-29

    申请号：US11496986

    申请日：2006-07-31

    申请人： Tanmay Kumar ,  S.B. Herner ,  Roy Scheuerlein ,  Christopher Petti

    发明人： Tanmay Kumar ,  S.B. Herner ,  Roy Scheuerlein ,  Christopher Petti

    IPC分类号： H01L21/8234

    CPC分类号： G11C11/5692 ,  G11C13/0069 ,  G11C17/14 ,  G11C17/165 ,  G11C2013/0073 ,  H01L27/101

    摘要： A nonvolatile memory cell comprising a diode formed of semiconductor material can store memory states by changing the resistance of the semiconductor material by application of a set pulse (decreasing resistance) or a reset pulse (increasing resistance.) In preferred embodiments, set pulses are applied with the diode under forward bias, while reset pulses are applied with the diode in reverse bias. By switching resistivity of the semiconductor material of the diode, a memory cell can be either one-time programmable or rewriteable, and can achieve two, three, four, or more distinct data states.

    摘要翻译： 包括由半导体材料形成的二极管的非易失性存储单元可以通过施加设置脉冲（降低电阻）或复位脉冲（增加电阻）来改变半导体材料的电阻来存储存储器状态。在优选实施例中，施加设定脉冲 二极管在正向偏置下，而复位脉冲以二极管反向施加。 通过切换二极管的半导体材料的电阻率，存储器单元可以是一次性可编程的或可重写的，并且可以实现两个，三个，四个或更多个不同的数据状态。

    Method of programming a monolithic three-dimensional memory
    6.
    发明申请
    Method of programming a monolithic three-dimensional memory 审中-公开
    编写单片三维存储器的方法

    公开(公告)号：US20060067127A1

    公开(公告)日：2006-03-30

    申请号：US10955049

    申请日：2004-09-30

    申请人： Luca Fasoli ,  Roy Scheuerlein ,  Alper Ilkbahar ,  En-Hsing Chen ,  Tanmay Kumar

    发明人： Luca Fasoli ,  Roy Scheuerlein ,  Alper Ilkbahar ,  En-Hsing Chen ,  Tanmay Kumar

    IPC分类号： G11C11/34 ,  G11C16/04

    CPC分类号： G11C16/12 ,  G11C16/16

    摘要： A method of programming a monolithic three-dimensional (3-D) memory having a plurality of levels of memory cells above a silicon substrate is disclosed. The method includes initializing a program voltage and program time interval; selecting a memory cell to be programmed within the three-dimensional memory having the plurality of levels of memory cells; applying a pulse having the program voltage and the program time interval to the selected memory cell; performing a read after write operation with respect to the selected memory cell to determine a measured threshold voltage value; and comparing the measured threshold voltage value to a minimum program voltage. In response to the comparison between the measured threshold voltage value and the minimum program voltage, the method further includes selectively applying at least one subsequent program pulse to the selected memory cell.

    摘要翻译： 公开了一种在硅衬底上编程具有多层存储单元的单片三维（3-D）存储器的方法。 该方法包括初始化程序电压和程序时间间隔; 选择要在具有多个级别的存储器单元的三维存储器内编程的存储器单元; 将具有编程电压和程序时间间隔的脉冲施加到所选存储单元; 在对所选择的存储单元进行写操作之后执行读取以确定测量的阈值电压值; 以及将所测量的阈值电压值与最小编程电压进行比较。 响应于测量的阈值电压值和最小编程电压之间的比较，该方法还包括选择性地将至少一个后续编程脉冲施加到所选存储单元。

    PUNCH-THROUGH DIODE STEERING ELEMENT
    9.
    发明申请
    PUNCH-THROUGH DIODE STEERING ELEMENT 有权
    PUNCH-THROUGH二极管转向元件

    公开(公告)号：US20110089391A1

    公开(公告)日：2011-04-21

    申请号：US12582509

    申请日：2009-10-20

    申请人： Andrei Mihnea ,  Deepak C. Sekar ,  George Samachisa ,  Roy Scheuerlein ,  Li Xiao

    发明人： Andrei Mihnea ,  Deepak C. Sekar ,  George Samachisa ,  Roy Scheuerlein ,  Li Xiao

    IPC分类号： H01L29/861 ,  H01L45/00 ,  H01L21/70

    CPC分类号： G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/72 ,  H01L27/24

    摘要： A storage system and method for forming a storage system that uses punch-through diodes as a steering element in series with a reversible resistivity-switching element is described. The punch-through diode allows bipolar operation of a cross-point memory array. The punch-through diode may have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. Therefore, it is compatible with bipolar switching in cross-point memory arrays having resistive switching elements. The punch-through diode may be a N+/P−/N+ device or a P+/N−/P+ device.

    摘要翻译： 描述了一种用于形成使用穿通二极管作为与可逆电阻率切换元件串联的转向元件的存储系统的存储系统和方法。 穿通二极管允许交叉点存储器阵列的双极性操作。 穿通二极管可具有对称的非线性电流/电压关系。 穿通二极管在选择的电池的高偏压下具有高电流，对于未选择的电池，在低偏压下具有低泄漏电流。 因此，它与具有电阻式开关元件的交叉点存储器阵列中的双极开关兼容。 穿通二极管可以是N + / P- / N +器件或P + / N- / P +器件。

    Three dimensional NAND memory
    10.
    发明授权
    Three dimensional NAND memory 有权
    三维NAND存储器

    公开(公告)号：US07848145B2

    公开(公告)日：2010-12-07

    申请号：US11691901

    申请日：2007-03-27

    申请人： Nima Mokhlesi ,  Roy Scheuerlein

    发明人： Nima Mokhlesi ,  Roy Scheuerlein

    IPC分类号： G11C16/04 ,  G11C5/02 ,  G11C5/06

    CPC分类号： H01L29/7926 ,  G11C16/0483 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792

    摘要： A monolithic, three dimensional NAND string includes a first memory cell located over a second memory cell, a select transistor, a first word line of the first memory cell, a second word line of the second memory cell, a bit line, a source line, and a select gate line of the select transistor. The first and the second word lines are not parallel to the bit line, and the first and the second word lines extend parallel to at least one of the source line and the select gate line.

    摘要翻译： 单片三维NAND串包括位于第二存储单元上的第一存储单元，选择晶体管，第一存储单元的第一字线，第二存储单元的第二字线，位线，源极线 ，以及选择晶体管的选择栅极线。 第一和第二字线不平行于位线，并且第一和第二字线平行于源极线和选择栅极线中的至少一个延伸。