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    Memory with high dielectric constant antifuses and method for using at low voltage
    1.
    发明申请
    Memory with high dielectric constant antifuses and method for using at low voltage 审中-公开
    高介电常数反熔丝的存储器和低电压使用的方法

    公开(公告)号：US20070069241A1

    公开(公告)日：2007-03-29

    申请号：US11173973

    申请日：2005-07-01

    Applicant: Xiaoyu Yang ,  Roy Scheuerlein ,  Feng Li ,  Albert Meeks

    Inventor： Xiaoyu Yang ,  Roy Scheuerlein ,  Feng Li ,  Albert Meeks

    IPC: H01L27/10 ,  H01L21/82

    CPC classification number: H01L45/12 ,  G11C17/00 ,  G11C17/16 ,  H01L23/5252 ,  H01L27/101 ,  H01L45/04 ,  H01L45/146 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A memory array having memory cells comprising a diode and an antifuse can be made smaller and programmed at lower voltage by using antifuse materials having higher dielectric constant and higher acceleration factor than silicon dioxide, and by using diodes having lower band gaps than silicon. Such memory arrays can be made to have long operating lifetimes by using the high acceleration factor and lower band gap materials. Antifuse materials having dielectric constants between 5 and 27, for example hafnium silicon oxynitride or hafnium silicon oxide are particularly effective. Diode materials with band gaps lower than silicon, such as germanium or a silicon-germanium alloy are particularly effective.

    Abstract translation: 通过使用具有比二氧化硅更高的介电常数和更高的加速因子的反熔丝材料，并且通过使用具有比硅更低的带隙的二极管，可以使具有包括二极管和反熔丝的存储单元的存储器阵列更小并且在较低的电压下编程。 这样的存储器阵列可以通过使用高加速因子和较低带隙材料而具有长的工作寿命。 具有介于5和27之间的介电常数的防腐材料，例如铪硅氮氧化物或氧化铪铪是特别有效的。 带隙低于硅的二极管材料，例如锗或硅 - 锗合金是特别有效的。

    PUNCH-THROUGH DIODE STEERING ELEMENT
    4.
    发明申请
    PUNCH-THROUGH DIODE STEERING ELEMENT 有权
    PUNCH-THROUGH二极管转向元件

    公开(公告)号：US20110089391A1

    公开(公告)日：2011-04-21

    申请号：US12582509

    申请日：2009-10-20

    Applicant: Andrei Mihnea ,  Deepak C. Sekar ,  George Samachisa ,  Roy Scheuerlein ,  Li Xiao

    Inventor： Andrei Mihnea ,  Deepak C. Sekar ,  George Samachisa ,  Roy Scheuerlein ,  Li Xiao

    IPC: H01L29/861 ,  H01L45/00 ,  H01L21/70

    CPC classification number: G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/72 ,  H01L27/24

    Abstract: A storage system and method for forming a storage system that uses punch-through diodes as a steering element in series with a reversible resistivity-switching element is described. The punch-through diode allows bipolar operation of a cross-point memory array. The punch-through diode may have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. Therefore, it is compatible with bipolar switching in cross-point memory arrays having resistive switching elements. The punch-through diode may be a N+/P−/N+ device or a P+/N−/P+ device.

    Abstract translation: 描述了一种用于形成使用穿通二极管作为与可逆电阻率切换元件串联的转向元件的存储系统的存储系统和方法。 穿通二极管允许交叉点存储器阵列的双极性操作。 穿通二极管可具有对称的非线性电流/电压关系。 穿通二极管在选择的电池的高偏压下具有高电流，对于未选择的电池，在低偏压下具有低泄漏电流。 因此，它与具有电阻式开关元件的交叉点存储器阵列中的双极开关兼容。 穿通二极管可以是N + / P- / N +器件或P + / N- / P +器件。

    Three dimensional NAND memory
    5.
    发明授权
    Three dimensional NAND memory 有权
    三维NAND存储器

    公开(公告)号：US07848145B2

    公开(公告)日：2010-12-07

    申请号：US11691901

    申请日：2007-03-27

    Applicant: Nima Mokhlesi ,  Roy Scheuerlein

    Inventor： Nima Mokhlesi ,  Roy Scheuerlein

    IPC: G11C16/04 ,  G11C5/02 ,  G11C5/06

    CPC classification number: H01L29/7926 ,  G11C16/0483 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792

    Abstract: A monolithic, three dimensional NAND string includes a first memory cell located over a second memory cell, a select transistor, a first word line of the first memory cell, a second word line of the second memory cell, a bit line, a source line, and a select gate line of the select transistor. The first and the second word lines are not parallel to the bit line, and the first and the second word lines extend parallel to at least one of the source line and the select gate line.

    Abstract translation: 单片三维NAND串包括位于第二存储单元上的第一存储单元，选择晶体管，第一存储单元的第一字线，第二存储单元的第二字线，位线，源极线 ，以及选择晶体管的选择栅极线。 第一和第二字线不平行于位线，并且第一和第二字线平行于源极线和选择栅极线中的至少一个延伸。

    Method of making three dimensional NAND memory
    6.
    发明授权
    Method of making three dimensional NAND memory 有权
    制作三维NAND存储器的方法

    公开(公告)号：US07514321B2

    公开(公告)日：2009-04-07

    申请号：US11691840

    申请日：2007-03-27

    Applicant: Nima Mokhlesi ,  Roy Scheuerlein

    Inventor： Nima Mokhlesi ,  Roy Scheuerlein

    IPC: H01L21/336

    CPC classification number: H01L27/115 ,  H01L27/0605 ,  H01L27/0688 ,  H01L27/11568 ,  H01L27/11582

    Abstract: A method of making a monolithic, three dimensional NAND string, includes forming a semiconductor active region of a first memory cell over a semiconductor active region of a second memory cell. The semiconductor active region of the first memory cell is a first pillar having a square or rectangular cross section when viewed from above, the first pillar being a first conductivity type semiconductor region located between second conductivity type semiconductor regions. The semiconductor active region of the second memory cell is a second pillar having a square or rectangular cross section when viewed from above, the second pillar located under the first pillar, the second pillar being a first conductivity type semiconductor region located between second conductivity type semiconductor regions. One second conductivity type semiconductor region in the first pillar contacts one second conductivity type semiconductor region in the second pillar.

    Abstract translation: 制造单片三维NAND串的方法包括在第二存储单元的半导体有源区上形成第一存储单元的半导体有源区。 第一存储单元的半导体有源区是从上方观察时具有正方形或矩形截面的第一柱，第一柱是位于第二导电型半导体区之间的第一导电型半导体区。 第二存储单元的半导体有源区是当从上方观察时具有正方形或矩形横截面的第二柱，位于第一柱下方的第二柱，第二柱是位于第二导电型半导体 地区。 第一柱中的一个第二导电类型半导体区域接触第二柱中的一个第二导电类型半导体区域。

    METHOD OF MAKING THREE DIMENSIONAL NAND MEMORY
    7.
    发明申请
    METHOD OF MAKING THREE DIMENSIONAL NAND MEMORY 有权
    制造三维NAND存储器的方法

    公开(公告)号：US20080242008A1

    公开(公告)日：2008-10-02

    申请号：US11691885

    申请日：2007-03-27

    Applicant: Nima Mokhlesi ,  Roy Scheuerlein

    Inventor： Nima Mokhlesi ,  Roy Scheuerlein

    IPC: H01L21/77

    CPC classification number: H01L27/11568 ,  H01L27/0605 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11582

    Abstract: A method of making a monolithic, three dimensional NAND string, includes forming a select transistor, forming a first memory cell over a second memory cell, forming a first word line for the first memory cell, forming a second word line for the second memory cell, forming a bit line, forming a source line, and forming a select gate line for the select transistor. The first and the second word lines are not parallel to the bit line, and the first and the second word lines extend parallel to at least one of the source line and the select gate line.

    Abstract translation: 制造单片三维NAND串的方法包括形成选择晶体管，在第二存储单元上形成第一存储单元，形成第一存储单元的第一字线，形成用于第二存储单元的第二字线 形成位线，形成源极线，并形成用于选择晶体管的选择栅极线。 第一和第二字线不平行于位线，并且第一和第二字线平行于源极线和选择栅极线中的至少一个延伸。

    Method for using a multi-use memory cell and memory array
    8.
    发明申请
    Method for using a multi-use memory cell and memory array 有权
    使用多用途存储单元和存储器阵列的方法

    公开(公告)号：US20070070690A1

    公开(公告)日：2007-03-29

    申请号：US11496984

    申请日：2006-07-31

    Applicant: Roy Scheuerlein ,  Tanmay Kumar

    Inventor： Roy Scheuerlein ,  Tanmay Kumar

    IPC: G11C11/14

    CPC classification number: G11C11/5692 ,  G11C11/005 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C17/14 ,  G11C2211/5641 ,  G11C2211/5646 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/76 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/148

    Abstract: A method for using a multi-use memory cell and memory array are disclosed. In one preferred embodiment, a memory cell is operable as a one-time programmable memory cell or a rewritable memory cell. The memory cell comprises a memory element comprising a semiconductor material configurable to one of at least three resistivity states, wherein a first resistivity state is used to represent a data state of the memory cell when the memory cell operates as a one-time programmable memory cell but not when the memory cell operates as a rewritable memory cell. A memory array with such memory cells is also disclosed. In another preferred embodiment, a memory cell is provided comprising a switchable resistance material, wherein the memory cell is operable in a first mode in which the memory cell is programmed with a forward bias and a second mode in which the memory cell is programmed with a reverse bias.

    Abstract translation: 公开了一种使用多用存储单元和存储器阵列的方法。 在一个优选实施例中，存储器单元可操作为一次性可编程存储器单元或可重写存储单元。 存储单元包括存储元件，其包括可配置为至少三种电阻率状态之一的半导体材料，其中当存储器单元作为一次可编程存储单元操作时，第一电阻率状态用于表示存储单元的数据状态 但是当存储器单元作为可重写存储单元时不起作用。 还公开了具有这种存储单元的存储器阵列。 在另一个优选实施例中，提供了一种包括可切换电阻材料的存储单元，其中存储单元可在第一模式中操作，其中存储单元用正向偏置和第二模式编程，其中存储单元用 反向偏差。

    Word line arrangement having multi-layer word line segments for three-dimensional memory array
    9.
    发明申请
    Word line arrangement having multi-layer word line segments for three-dimensional memory array 有权
    具有用于三维存储器阵列的多层字线段的字线布置

    公开(公告)号：US20050180247A1

    公开(公告)日：2005-08-18

    申请号：US11103185

    申请日：2005-04-11

    Applicant: Roy Scheuerlein

    Inventor： Roy Scheuerlein

    IPC: G11C8/08 ,  H01L27/115 ,  G11C8/00

    CPC classification number: H01L27/115 ,  G11C8/08

    Abstract: A three-dimensional (3D) passive element memory cell array provides short word lines while still maintaining a small support circuit area for efficiency. Short, low resistance word line segments on two or more word line layers are connected together in parallel to form a given word line without use of segment switch devices between the word line segments. A shared vertical connection preferably connects the word line segments together and connects to a word line driver circuit disposed generally below the array near the word line. Each word line driver circuit preferably couples its word line either to an associated one of a plurality of selected bias lines or to an unselected bias line associated with the driver circuit, which selected bias lines are themselves decoded to provide for an efficient multi-headed word line decoder.

    Abstract translation: 三维（3D）无源元件存储单元阵列提供短字线，同时仍然保持小的支持电路面积的效率。 两个或多个字线层上的短路，低电阻字线段并行连接在一起，以形成给定字线，而不使用字线段之间的段开关器件。 共享垂直连接优选地将字线段连接在一起并连接到通常位于字线附近的阵列下方设置的字线驱动电路。 每个字线驱动器电路优选地将其字线耦合到多个所选择的偏置线中的相关联的一条或者与驱动器电路相关联的未选择的偏置线，所选择的偏置线本身被解码以提供有效的多头字 线解码器。

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