公开(公告)号：US09928207B1

公开(公告)日：2018-03-27

申请号：US14869107

申请日：2015-09-29

Applicant: Amazon Technologies, Inc.

Inventor： Adi Habusha ,  Nafea Bshara ,  Itay Poleg ,  Erez Izenberg ,  Guy Nakibly ,  Matthew Shawn Wilson

IPC: G06F13/00 ,  G06F13/42 ,  G06F13/40 ,  G06F13/38

CPC classification number: G06F13/4282 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/404 ,  G06F13/4221

Abstract: Provided are systems and methods for generating transactions with a configurable port. In some implementations, a peripheral device is provided. The peripheral device comprises a configurable port. In some implementations, the configurable port may be configured to receive a first transaction. In these implementations, the first transactions may include an address. The address may include a transaction attribute. In some implementations, the configurable port may extract the transaction attribute and a transaction address from the address. The configurable port may further generate a second transaction that includes the transaction attribute and the transaction address. The configurable port may also transmit the second transaction.

公开(公告)号：US12204481B2

公开(公告)日：2025-01-21

申请号：US18383833

申请日：2023-10-25

Applicant: Amazon Technologies, Inc.

Inventor： Islam Atta ,  Christopher Joseph Pettey ,  Asif Khan ,  Robert Michael Johnson ,  Mark Bradley Davis ,  Erez Izenberg ,  Nafea Bshara ,  Kypros Constantinides

IPC: G06F13/40 ,  G06F9/445 ,  G06F13/42 ,  G06F15/78

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

公开(公告)号：US20240232117A9

公开(公告)日：2024-07-11

申请号：US18383833

申请日：2023-10-25

Applicant: Amazon Technologies, Inc.

Inventor： Islam Atta ,  Christopher Joseph Pettey ,  Asif Khan ,  Robert Michael Johnson ,  Mark Bradley Davis ,  Erez Izenberg ,  Nafea Bshara ,  Kypros Constantinides

IPC: G06F13/40 ,  G06F9/445 ,  G06F13/42 ,  G06F15/78

CPC classification number: G06F13/4068 ,  G06F9/44505 ,  G06F13/4282 ,  G06F15/7867 ,  G06F15/7871

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

公开(公告)号：US11960392B1

公开(公告)日：2024-04-16

申请号：US17643127

申请日：2021-12-07

Applicant: Amazon Technologies, Inc.

Inventor： Guy Nakibly ,  Dan Saad ,  Yaniv Shapira ,  Erez Izenberg

IPC: G06F13/14 ,  G06F9/46 ,  G06F12/02 ,  G06F13/16 ,  G06F13/38 ,  G06F13/42 ,  G11C11/408

CPC classification number: G06F12/0238 ,  G06F9/467 ,  G06F12/0292 ,  G06F13/1621 ,  G06F13/38 ,  G06F13/4221 ,  G11C11/4087

Abstract: A first configurable address decoder can be coupled between a source node and a first interconnect fabric, and a second address decoder can be coupled between the first interconnect fabric and a second interconnect fabric. The first address decoder can be configured with a first address mapping table that can map a first set of address ranges to a first set of target nodes connected to the first interconnect fabric. The second address decoder can be configured with a second address mapping table that can map a second set of address ranges to a second set of target nodes connected to the second interconnect fabric. The second address decoder can be part of the first set of target nodes. The first address decoder and the second address decoder can be configured or re-configured to determine different routes for a transaction from the source node to a target node in the second set of target nodes via the first and second interconnect fabrics.

公开(公告)号：US11853253B1

公开(公告)日：2023-12-26

申请号：US14983335

申请日：2015-12-29

Applicant: Amazon Technologies, Inc.

Inventor： Nafea Bshara ,  Leah Shalev ,  Erez Izenberg ,  Georgy Machulsky ,  Guy Nakibly

IPC: G06F15/173 ,  H04L67/1097

CPC classification number: G06F15/17331 ,  H04L67/1097

Abstract: Apparatus and methods are disclosed herein for remote, direct memory access (RDMA) technology that enables direct memory access from one host computer memory to another host computer memory over a physical or virtual computer network. In one example, RDMA functionality is provided by combining a host executing instructions for RDMA software applications with dedicated hardware accelerator, where the host has access to substantially all RDMA connection context (e.g., configuration, status, state machine, counters, etc.) and a hardware accelerator stores a portion of the context information for a set of currently active transactions. The hardware accelerator derives a transaction identifier from header information in received RDMA packets and performs a local RDMA operation using at least a portion of the received data, a destination address of the location RDMA operation being based at least in part on a memory address determined using the transaction identifier.

公开(公告)号：US20230409514A1

公开(公告)日：2023-12-21

申请号：US18239694

申请日：2023-08-29

Applicant: Amazon Technologies, Inc.

Inventor： Nafea Bshara ,  Leah Shalev ,  Erez Izenberg ,  Georgy Machulsky ,  Guy Nakibly

IPC: G06F15/173 ,  H04L67/1097

CPC classification number: G06F15/17331 ,  H04L67/1097

Abstract: Apparatus and methods are disclosed herein for remote, direct memory access (RDMA) technology that enables direct memory access from one host computer memory to another host computer memory over a physical or virtual computer network. In one example, RDMA functionality is provided by combining a host executing instructions for RDMA software applications with dedicated hardware accelerator, where the host has access to substantially all RDMA connection context (e.g., configuration, status, state machine, counters, etc.) and a hardware accelerator stores a portion of the context information for a set of currently active transactions. The hardware accelerator derives a transaction identifier from header information in received RDMA packets and performs a local RDMA operation using at least a portion of the received data, a destination address of the location RDMA operation being based at least in part on a memory address determined using the transaction identifier.

公开(公告)号：US20230018032A1

公开(公告)日：2023-01-19

申请号：US17952144

申请日：2022-09-23

Applicant: Amazon Technologies, Inc.

Inventor： Islam Atta ,  Christopher Joseph Pettey ,  Asif Khan ,  Robert Michael Johnson ,  Mark Bradley Davis ,  Erez Izenberg ,  Nafea Bshara ,  Kypros Constantinides

IPC: G06F13/40 ,  G06F9/445 ,  G06F13/42 ,  G06F15/78

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

公开(公告)号：US11483296B1

公开(公告)日：2022-10-25

申请号：US16917367

申请日：2020-06-30

Applicant: Amazon Technologies, Inc.

Inventor： Ron Diamant ,  Nafea Bshara ,  Leah Shalev ,  Erez Izenberg

IPC: H04L9/40 ,  H04L9/32 ,  H04L9/08 ,  H04L9/14 ,  G09C1/00

Abstract: A hardware security accelerator includes a configurable parser that is configured to receive a packet and to extract from the packet headers associated with a set of protocols. The security accelerator also includes a packet type detection unit to determine a type of the packet in response to the set of protocols and to generate a packet type identifier indicative of the type of the packet. A configurable security unit includes a configuration unit and a configurable security engine. The configuration unit configures the configurable security engine according to the type of the packet and to content of at least one of the headers extracted from the packet. The configurable security engine performs security processing of the packet to provide at least one security result.

公开(公告)号：US11467998B1

公开(公告)日：2022-10-11

申请号：US17203231

申请日：2021-03-16

Applicant: Amazon Technologies, Inc.

Inventor： Erez Izenberg ,  Said Bshara ,  Jonathan Cohen ,  Avigdor Segal

IPC: G06F13/20 ,  G06F13/42 ,  G06F13/28 ,  G06F15/173 ,  G06F15/78 ,  G06F9/46

Abstract: Techniques for low-latency packet processing are disclosed. A network device receives a first set of write transactions including a first set of data segments corresponding to a first DMA descriptor from a host. The network device receives a second set of write transactions including a second set of data segments corresponding to a second DMA descriptor from the host. The network device detects that the first set of data segments have been written. In response to detecting that the first set of data segments have been written, and prior to completely writing the second set of data segments and to receiving a packet notifier from the host, the network device processes the first DMA descriptor.

公开(公告)号：US11294841B1

公开(公告)日：2022-04-05

申请号：US16985056

申请日：2020-08-04

Applicant: Amazon Technologies, Inc.

Inventor： Adiel Sarusi ,  Ron Diamant ,  Ori Weber ,  Erez Izenberg

IPC: G06F13/40 ,  G06F13/16 ,  G06F13/42

Abstract: Techniques disclosed herein relate to dynamically configurable multi-stage pipeline processing units. In one embodiment, a circuit includes a plurality of processing engines and a plurality of switches. Each of the plurality of processing engines includes an input port and an output port. Each of the plurality of switches comprises two input ports and two output ports. For each processing engine, the input port of the processing engine is electrically coupled to one of the switches, the output port of the processing engine is electrically coupled to another one of the switches, and the input port of the processing engine is electrically coupled to the output port of each of the processing engines by the switches.