-
公开(公告)号：US20160292094A1
公开(公告)日：2016-10-06
申请号：US14676174
申请日：2015-04-01
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Brijesh Tripathi , Kiran Kattel , Rakesh L. Notani , Fabien S. Faure , Sukalpa Biswas , Kai Lun Hsiung , Neeraj Parik , Venkata Ramana Malladi , Shiva Kumar , Chaitanya Polapragada , Allen Kim
IPC: G06F13/16
CPC classification number: G06F13/1668 , G06F13/1689 , Y02D10/14
Abstract: An apparatus and method for encoding data are disclosed that may allow for performing periodic calibration operations on a communication link. A controller may determine multiple possible values for a reference voltage used with the communication link based on an initial value. Calibration operations may be performed using each possible value, and the results of the operations scored based on the width of data eyes measured during the calibration operations. The controller may then select a new value for the reference voltage from the multiple possible values dependent upon the scores of each of the multiple possible values.
Abstract translation: 公开了一种用于编码数据的装置和方法，其可以允许在通信链路上执行周期性校准操作。 控制器可以基于初始值来确定与通信链路一起使用的参考电压的多个可能值。 可以使用每个可能的值执行校准操作，并且基于在校准操作期间测量的数据眼睛的宽度来评估操作的结果。 然后，控制器可以根据多个可能值中的每一个的分数从多个可能值中选择参考电压的新值。
-
公开(公告)号：US20160209866A1
公开(公告)日：2016-07-21
申请号：US14597321
申请日：2015-01-15
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Neeraj Parik , Sukalpa Biswas
Abstract: A method and apparatus for calibration of a clock signal used in data transmission is disclosed. The method includes a calibration having coarse and fine grain procedures. The coarse grain procedure begins from the center of a current eye and performs reads while decrementing the delay provided to the clock signal until at least one bit fails. This is repeated, from the center of the eye, incrementing until again at least one bit fails. The lower and upper last passing points are recorded. A fine grain procedure includes performing reads while decrementing, from the lower last passing point, recording points at which each bit fails until all fail. The fine grain procedure further includes incrementing, from the upper last passing point, recording points at which each bit fails until fail. Thereafter, a clock delay corresponding to the center of the new eye is determined based on the calibration data.
Abstract translation: 公开了一种用于校准数据传输中使用的时钟信号的方法和装置。 该方法包括具有粗和细晶粒程序的校准。 粗粒度程序从当前眼睛的中心开始，并且在递减提供给时钟信号的延迟时执行读取，直到至少一个位失败。 这从眼睛的中心重复，直到再次至少一个位失败。 记录上下通过点。 细粒度过程包括从最下一个通过点向下递减执行读取，每个位失败的记录点直到全部失败。 细粒度过程还包括从上一个最后通过点增加每个位故障直到失败的记录点。 此后，基于校准数据确定与新眼睛的中心相对应的时钟延迟。
-
公开(公告)号：US09390681B2
公开(公告)日：2016-07-12
申请号：US14023418
申请日：2013-09-10
Applicant: APPLE INC.
Inventor： Ulrich T. Barnhoefer , Robert E. Jeter
CPC classification number: G09G5/10 , G09G3/3406 , G09G3/3607 , G09G2320/0271 , G09G2320/0626 , G09G2320/0646 , G09G2360/16
Abstract: Systems, methods, and devices are provided for temporal filtering of tone mapping slopes used in adjusting the power consumed by a backlight of an electronic display. One such method involves computing a current first target slope of an intermediate tone mapping function based at least in part on characteristics of a current image frame and temporally filtering the current first target slope to obtain a current first transition slope. A current backlight intensity of the display and a current final tone mapping function may be determined based at least in part on the current first transition slope. The current final tone mapping function may be applied to the current image frame or a subsequent image frame.
Abstract translation: 提供了系统，方法和装置，用于对调整电子显示器背光消耗的功率所使用的色调映射斜率进行时间滤波。 一种这样的方法包括至少部分地基于当前图像帧的特性来计算中间色调映射函数的当前第一目标斜率，并且对当前第一目标斜率进行暂时滤波以获得当前的第一转变斜率。 可以至少部分地基于当前的第一转变斜率来确定显示器的当前背光强度和当前最终色调映射功能。 当前的最终色调映射功能可以应用于当前图像帧或后续图像帧。
-
公开(公告)号：US20140078192A1
公开(公告)日：2014-03-20
申请号：US14023418
申请日：2013-09-10
Applicant: APPLE INC.
Inventor： Ulrich T. Barnhoefer , Robert E. Jeter
IPC: G09G3/34
CPC classification number: G09G5/10 , G09G3/3406 , G09G3/3607 , G09G2320/0271 , G09G2320/0626 , G09G2320/0646 , G09G2360/16
Abstract: Systems, methods, and devices are provided for temporal filtering of tone mapping slopes used in adjusting the power consumed by a backlight of an electronic display. One such method involves computing a current first target slope of an intermediate tone mapping function based at least in part on characteristics of a current image frame and temporally filtering the current first target slope to obtain a current first transition slope. A current backlight intensity of the display and a current final tone mapping function may be determined based at least in part on the current first transition slope. The current final tone mapping function may be applied to the current image frame or a subsequent image frame.
Abstract translation: 提供了系统，方法和装置，用于对调整电子显示器背光消耗的功率所使用的色调映射斜率进行时间滤波。 一种这样的方法包括至少部分地基于当前图像帧的特性来计算中间色调映射函数的当前第一目标斜率，并且对当前第一目标斜率进行暂时滤波以获得当前的第一转变斜率。 可以至少部分地基于当前的第一转变斜率来确定显示器的当前背光强度和当前最终色调映射功能。 当前的最终色调映射功能可以应用于当前图像帧或后续图像帧。
-
公开(公告)号：US20240295976A1
公开(公告)日：2024-09-05
申请号：US18658740
申请日：2024-05-08
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Jingkui Zheng , Ritesh J. Shah , Veera Chockalingam , Naveen Kumar Korada
IPC: G06F3/06 , G11C11/4076 , G11C11/4096 , G11C29/50
CPC classification number: G06F3/0632 , G06F3/0614 , G06F3/0658 , G06F3/0673 , G11C11/4076 , G11C11/4096 , G11C29/50
Abstract: Memory calibration with a margin check is disclosed. A memory subsystem includes a memory and a memory controller coupled to the memory. The memory controller includes a calibration circuit configured to perform, during an initialization process, horizontal memory calibrations for ones of a plurality of performance states and to determine and store, in a storage circuit, information indicative of a set of differences between calibration results for pairs of the plurality of performance states. The memory controller is further configured to, subsequent to the initialization process and in response to a change from a first one of the plurality of performance states to a second one of the plurality of performance states set initial memory parameters for the second performance state based on the set of differences. Thereafter, operation begins in the second performance state without performing an initial horizontal calibration.
-
Patent Agency Ranking
公开(公告)号：US12014060B2
公开(公告)日：2024-06-18
申请号：US17929212
申请日：2022-09-01
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Jingkui Zheng , Ritesh J. Shah , Veera Chockalingam , Naveen Kumar Korada
IPC: G11C29/00 , G06F3/06 , G11C11/4076 , G11C11/4096 , G11C29/50
CPC classification number: G06F3/0632 , G06F3/0614 , G06F3/0658 , G06F3/0673 , G11C11/4076 , G11C11/4096 , G11C29/50
Abstract: Memory calibration with a margin check is disclosed. A memory subsystem includes a memory and a memory controller coupled to the memory. The memory controller includes a calibration circuit configured to perform, during an initialization process, horizontal memory calibrations for ones of a plurality of performance states and to determine and store, in a storage circuit, information indicative of a set of differences between calibration results for pairs of the plurality of performance states. The memory controller is further configured to, subsequent to the initialization process and in response to a change from a first one of the plurality of performance states to a second one of the plurality of performance states set initial memory parameters for the second performance state based on the set of differences. Thereafter, operation begins in the second performance state without performing an initial horizontal calibration.
-
公开(公告)号：US20220189519A1
公开(公告)日：2022-06-16
申请号：US17646741
申请日：2022-01-03
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Rakesh L. Notani , Kai Lun Hsiung , Venkata Ramana Malladi , Rahul Ranjan , Naveen Kumar Korada
Abstract: A memory subsystem and method for performing calibrations therein is disclosed. A memory subsystem includes a memory controller coupled to a memory by a plurality of signal paths. The memory controller is configured to perform an initial calibration to determine respective eye patterns corresponding to the ones of the plurality of signal paths. For a subsequent calibrations, updated eye patterns are determined for a subset of the plurality of signal paths. Remaining ones of the plurality of signal paths (not included in the subset), are not active during the subsequent calibrations. Updated eye patterns for the remaining ones of the plurality of signal paths are determined based on information obtained during the initial calibration and information from signal paths in the subset designated proxies for the remaining ones of the plurality of signal paths.
-
公开(公告)号：US10991403B2
公开(公告)日：2021-04-27
申请号：US16277804
申请日：2019-02-15
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Rakesh L. Notani , Venkata R. Malladi
IPC: G11C7/22
Abstract: A method and apparatus for performing memory calibration with endpoint replay is disclosed. A first calibration of a data strobe signal in a memory subsystem is performed. The first calibration includes determining initial values of first and second endpoints indicative of first and second delay values, respectively, applied to the data strobe signal. A second calibration of the data strobe signal is performed around these endpoints, within a range thereof that is less than a full range there between. Based on the second calibration, the endpoints are adjusted.
-
公开(公告)号：US20200266810A1
公开(公告)日：2020-08-20
申请号：US16277263
申请日：2019-02-15
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Rakesh L. Notani , Kai Lun Hsiung , Yanzhe Liu
IPC: H03K5/156 , H03K3/017 , G11C11/409
Abstract: A method and apparatus for performing duty cycle correction with read/write calibrations is disclosed. A first calibration is performed in a memory subsystem having a memory and a memory controller. The first calibration includes conveying a first clock signal from the memory controller to the memory, and determining the duty cycle of the first clock signal. If the duty cycle is not within a specified range, the duty cycle is adjusted and the process repeated. After the duty cycle of the first clock signal is within the specified range, a second calibration is performed, the second calibration including conveying a second clock signal from the memory to the memory controller. The duty cycle of the first clock signal may be further adjusted based on the second calibration.
-
公开(公告)号：US10402121B2
公开(公告)日：2019-09-03
申请号：US15849945
申请日：2017-12-21
Applicant: Apple Inc.
Inventor： Rakesh L. Notani , Robert E. Jeter
IPC: G06F3/06
Abstract: A method and apparatus for performing performance state changes are disclosed. A power management circuit may be configured to receive requests for changes to first and second performance states for at least at least one memory of a plurality of memories. In response to a determination that a change to the first performance state is in progress, when the request to change to the second performance state is received, the power management controller may send a notification to a controller coupled to the memories. The controller may halt scheduling of memory interface calibration operations for the at least one memory based on the notification.
-
-
-
-
-
-
-
-
-
Search Results
60
records
(took 0.016 seconds)
