公开(公告)号：US20230082091A1

公开(公告)日：2023-03-16

申请号：US17934976

申请日：2022-09-23

Applicant: Apple Inc.

Inventor： Ramana V. Rachakonda ,  Rohit K. Gupta ,  Brad W. Simeral ,  Peter F. Holland

IPC: G06F1/3287 ,  G06F1/3228

Abstract: In an embodiment, a system may include one or more processors forming central processing units (CPUs) in the system, a display controller configured to display frames on a display device, a memory controller configured to control a memory, and a power management circuit. The power management circuit may be configured to establish one of a plurality of power states in the system. In a first power state, the display controller and the memory controller are powered on while the CPUs are powered off. The display controller may be configured to read a plurality of prerendered frames from the memory and display the plurality of prerendered frames at times specified for each of the plurality of prerendered frames.

公开(公告)号：US20230067307A1

公开(公告)日：2023-03-02

申请号：US17462777

申请日：2021-08-31

Applicant: Apple Inc.

Inventor： Rohit Natarajan ,  Jurgen M. Schulz ,  Christopher D. Shuler ,  Rohit K. Gupta ,  Thomas T. Zou ,  Srinivasa Rangan Sridharan

IPC: G06F12/0802

Abstract: An apparatus includes a cache controller circuit and a cache memory circuit that further includes cache memory having a plurality of cache lines. The cache controller circuit may be configured to receive a request to reallocate a portion of the cache memory circuit that is currently in use. This request may identify an address region corresponding to one or more of the cache lines. The cache controller circuit may be further configured, in response to the request, to convert the one or more cache lines to directly-addressable, random-access memory (RAM) by excluding the one or more cache lines from cache operations.

公开(公告)号：US20230064187A1

公开(公告)日：2023-03-02

申请号：US17455321

申请日：2021-11-17

Applicant: Apple Inc.

Inventor： Rohit K. Gupta ,  Gregory S. Mathews ,  Harshavardhan Kaushikkar ,  Jeonghee Shin ,  Rohit Natarajan

IPC: H04L12/927 ,  H04L12/801 ,  H04L12/825

Abstract: Techniques are disclosed relating to merging virtual communication channels in a portion of a computing system. In some embodiments, a communication fabric routes first and second classes of traffic with different quality-of-service parameters, using a first virtual channel for the first class and a second virtual channel for the second class. In some embodiments, a memory controller communicates, via the fabric, using a merged virtual channel configured to handle traffic from both the first virtual channel and the second virtual channel. In some embodiments, the system limits the rate at which an agent is allowed to transmit requests of the second class of traffic, but requests by the agent for the first class of traffic are not rate limited. Disclosed techniques may improve independence of virtual channels, relative to sharing the same channel in an entire system, without unduly increasing complexity.

公开(公告)号：US11594189B2

公开(公告)日：2023-02-28

申请号：US17368522

申请日：2021-07-06

Applicant: Apple Inc.

Inventor： Prabhu Rajamani ,  Liang Deng ,  Oren Kerem ,  Meir Harar ,  Ido Yaacov Soffair ,  Assaf Menachem ,  John H. Kelm ,  Rohit K. Gupta

IPC: G09G3/34

Abstract: Throttling circuitry may throttle the backlight reconstruction via backlight reconstruction and compensation circuitry in a display pipeline when power may be limited. This throttling of the display pipeline may limit a number of cycles that may be used for performing backlight reconstruction and compensation.

公开(公告)号：US20230014545A1

公开(公告)日：2023-01-19

申请号：US17949834

申请日：2022-09-21

Applicant: Apple Inc.

Inventor： Ramana V. Rachakonda ,  Peter F. Holland ,  Rohit K. Gupta ,  Brad W. Simeral

IPC: G06F1/3234 ,  G09G3/20 ,  G06F1/3218 ,  G06F1/18

Abstract: An electronic device may include a display panel. When content of an image frame is expected to consume relatively higher amounts of power, a controller of the electronic device may operate a switch to change a power supply of the display panel to be a power management integrated circuit of the electronic device. However, when content of an image frame is expected to consume relatively less amounts of power, the controller may operate the switch to change the power supply of the display panel to be a power supply of an electronic display, such as a power supply used to power driver circuitry of the electronic display.

公开(公告)号：US11500448B2

公开(公告)日：2022-11-15

申请号：US17015288

申请日：2020-09-09

Applicant: Apple Inc.

Inventor： Ramana V. Rachakonda ,  Rohit K. Gupta ,  Brad W. Simeral ,  Peter F. Holland

IPC: G06F1/32 ,  G06F1/3287 ,  G06F1/3228 ,  H04B17/318

Abstract: In an embodiment, a system may include one or more processors forming central processing units (CPUs) in the system, a display controller configured to display frames on a display device, a memory controller configured to control a memory, and a power management circuit. The power management circuit may be configured to establish one of a plurality of power states in the system. In a first power state, the display controller and the memory controller are powered on while the CPUs are powered off. The display controller may be configured to read a plurality of prerendered frames from the memory and display the plurality of prerendered frames at times specified for each of the plurality of prerendered frames.

公开(公告)号：US20140304441A1

公开(公告)日：2014-10-09

申请号：US13859000

申请日：2013-04-09

Applicant: APPLE INC.

Inventor： Deniz Balkan ,  Gurjeet S. Saund ,  Joseph P. Bratt ,  Kevin C. Wong ,  Manu Gulati ,  Rohit K. Gupta

IPC: G06F13/38

CPC classification number: G06F13/385

Abstract: Embodiments of a bridge circuit and system are disclosed that may allow converting transactions from one communication protocol to another. The bridge circuit may be coupled to a first bus employing a first communication protocol, and a second bus employing a second communication protocol. The second bus may include a plurality of virtual channels. The bridge circuit may be configured to receive transactions over the first bus, and convert the transactions to the second communication protocol, and to assign the converted transaction to one of the plurality of virtual channels. The bridge circuit may be further configured store the converted transaction. A plurality of limited throughput signals may be generated by the bridge circuit dependent upon a number of available credits for the plurality of virtual channels.

Abstract translation: 公开了桥接电路和系统的实施例，其可以允许将事务从一个通信协议转换到另一个通信协议。 桥接电路可以耦合到采用第一通信协议的第一总线，以及采用第二通信协议的第二总线。 第二总线可以包括多个虚拟通道。 桥接电路可以被配置为通过第一总线接收事务，并将事务转换为第二通信协议，并将转换的事务分配给多个虚拟通道中的一个。 可以进一步配置桥接电路来存储转换的事务。 取决于多个虚拟信道的可用信用数量，桥电路可以产生多个有限吞吐量信号。