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    CONFIGURABLE MOTION ESTIMATION SEARCH SYSTEMS AND METHODS
    33.
    发明申请
    CONFIGURABLE MOTION ESTIMATION SEARCH SYSTEMS AND METHODS 审中-公开

    公开(公告)号：US20170094293A1

    公开(公告)日：2017-03-30

    申请号：US14871848

    申请日：2015-09-30

    Applicant: Apple Inc.

    Inventor： Jim C. Chou ,  Mark P. Rygh ,  Guy Côté

    IPC: H04N19/42 ,  H04N19/103 ,  H04N19/182 ,  H04N19/186 ,  H04N19/139 ,  H04N19/147

    CPC classification number: H04N19/439 ,  H04N19/109 ,  H04N19/139 ,  H04N19/147 ,  H04N19/156 ,  H04N19/157 ,  H04N19/17 ,  H04N19/182 ,  H04N19/186

    Abstract: System and method for improving operational efficiency of a video encoding pipeline used to encode image data. The video encoding pipeline includes a motion estimation setup block, which dynamically adjusts a setup configuration of the motion estimation block based at least in part on operational parameters of the video encoding pipeline and select an initial candidate inter-frame prediction mode based at least on the setup configuration, a full-pel motion estimation block, which determines an intermediate candidate inter-frame prediction mode by performing a motion estimation search based on the initial candidate inter-frame prediction mode, a sub-pel motion estimation block, which determines a final candidate inter-frame prediction by performing a motion estimation search based on the intermediate candidate inter-frame prediction mode, and a mode decision block, which determines a rate-distortion cost associated with the final candidate inter-frame prediction mode and determines a prediction mode used to prediction encoding the image data.

    Processing order in block processing pipelines
    34.
    发明授权
    Processing order in block processing pipelines 有权
    块处理流程中的处理顺序

    公开(公告)号：US09218639B2

    公开(公告)日：2015-12-22

    申请号：US14039820

    申请日：2013-09-27

    Applicant: Apple Inc.

    Inventor： Guy Cote ,  Mark P. Rygh ,  Timothy John Millet ,  Jim C. Chou ,  Joseph J. Cheng

    IPC: G06T15/00 ,  G06T1/20 ,  H04N19/61 ,  H04N19/423 ,  H04N19/436

    CPC classification number: G06T1/20 ,  H04N19/423 ,  H04N19/436 ,  H04N19/61

    Abstract: A knight's order processing method for block processing pipelines in which the next block input to the pipeline is taken from the row below and one or more columns to the left in the frame. The knight's order method may provide spacing between adjacent blocks in the pipeline to facilitate feedback of data from a downstream stage to an upstream stage. The rows of blocks in the input frame may be divided into sets of rows that constrain the knight's order method to maintain locality of neighbor block data. Invalid blocks may be input to the pipeline at the left of the first set of rows and at the right of the last set of rows, and the sets of rows may be treated as if they are horizontally arranged rather than vertically arranged, to maintain continuity of the knight's order algorithm.

    Abstract translation: 一种用于块处理管线的骑士订单处理方法，其中从管线的下一个块输入下一个块，并且在该帧中从左侧获取一个或多个列。 骑士的订单方法可以在管道中的相邻块之间提供间隔，以便于数据从下游阶段到上游阶段的反馈。 输入帧中的块行可以被划分为限制骑士命令方法以维持相邻块数据的位置的行的集合。 无效的块可以被输入到第一组行的左侧和最后一组行的右侧的流水线，并且这些行的集合可以被视为水平排列而不是垂直排列，以保持连续性 的骑士秩序算法。

    PARALLEL ENCODING OF BYPASS BINARY SYMBOLS IN CABAC ENCODER
    35.
    发明申请
    PARALLEL ENCODING OF BYPASS BINARY SYMBOLS IN CABAC ENCODER 有权
    并行编码CABAC编码器中的旁路二进制符号

    公开(公告)号：US20150092833A1

    公开(公告)日：2015-04-02

    申请号：US14039880

    申请日：2013-09-27

    Applicant: Apple Inc.

    Inventor： Weichun Ku ,  Jim C. Chou

    IPC: H04N19/13 ,  H04N19/70 ,  H04N19/103 ,  H04N19/176

    CPC classification number: H04N19/176 ,  H04N19/129 ,  H04N19/13 ,  H04N19/40 ,  H04N19/439 ,  H04N19/463

    Abstract: A video encoder may include a context-adaptive binary arithmetic coding (CABAC) encode component that converts each syntax element of a representation of a block of pixels to binary code, serializes it, and codes it mathematically with its probability model, after which the resulting bit stream is output. When the probability of a bin being coded with one of two possible symbols is one-half, the bin may be coded using bypass bin coding mode rather than a more compute-intensive regular bin coding mode. The CABAC encoder may code multiple consecutive bypass bins in a series of cascaded processing units during a single processing cycle (e.g., a regular bin coding cycle). Intermediate outputs of each processing unit may be coupled to inputs of the next processing unit. A resolver unit may accept intermediate outputs of the processing units and generate final output bits for the bypass bins.

    Abstract translation: 视频编码器可以包括上下文自适应二进制算术编码（CABAC）编码组件，其将像素块的表示的每个语法元素转换为二进制码，将其序列化，并用其概率模型对其进行数学编码，之后得到 输出位流。 当用两个可能符号中的一个编码一个bin的概率为一半时，可以使用旁路箱编码模式而不是更计算密集的常规二进制编码模式对该bin进行编码。 CABAC编码器可以在单个处理周期（例如，常规bin编码周期）期间对一系列级联处理单元中的多个连续旁路仓进行编码。 每个处理单元的中间输出可以耦合到下一处理单元的输入。 解算器单元可以接收处理单元的中间输出并且产生旁路箱的最终输出位。

    Optical Crosstalk Compensation for Foveated Display
    36.
    发明申请
    Optical Crosstalk Compensation for Foveated Display 有权

    公开(公告)号：US20240404461A1

    公开(公告)日：2024-12-05

    申请号：US18429079

    申请日：2024-01-31

    Applicant: Apple Inc.

    Inventor： Shereef Shehata ,  Jim C. Chou ,  Sheng Zhang ,  Shengchang Cai

    IPC: G09G3/3208 ,  G06F3/01

    Abstract: Systems and methods are provided for using an optical crosstalk compensation (OXTC) block to compensate for optical crosstalk resulted from a combination of viewing angle change across field of view (FoV), color filter (CF) crosstalk, and the OLED various angle color shift (VACS) of a foveated electronic display. One or more two-dimensional (2D) OXTC factor maps are used to determine OXTC factors for input image data of the OXTC block, and the OXTC factors are updated on a per frame basis. Offset values are determined using a parallel architecture and used to determine the OXTC factors. Compensation weights are used to determine weighted OXTC factors to improve processing efficiency. Output image data are obtained by applying the weighted OXTC factors to the input image data.

    Hierarchical grid interpolation systems and methods
    37.
    发明授权
    Hierarchical grid interpolation systems and methods 有权

    公开(公告)号：US12106444B2

    公开(公告)日：2024-10-01

    申请号：US17356216

    申请日：2021-06-23

    Applicant: Apple Inc.

    Inventor： Jim C. Chou ,  Jian Zhou

    IPC: G06T3/18 ,  G06T3/04 ,  G06T3/4007

    CPC classification number: G06T3/18 ,  G06T3/04 ,  G06T3/4007

    Abstract: An electronic device may include an electronic display to display an image based on processed image data. The electronic device may also include image processing circuitry to determine a hierarchical grid having multiple grid points divided into grid partitions. A first set of grid points associated with a first set of grid partitions may include a first set of mappings to corresponding coordinates of input image data in a source frame. The image processing circuitry may also interpolate between the first set of grid points to determine a second set of grid points of having a second set of mappings to corresponding coordinates of the input image data based on the first set of mappings. The image processing circuitry may also generate the processed image data by applying the first set of mappings and the second set of mappings to the input image data.

    NEURAL NETWORK-BASED IMAGE PROCESSING WITH ARTIFACT COMPENSATION
    38.
    发明公开
    NEURAL NETWORK-BASED IMAGE PROCESSING WITH ARTIFACT COMPENSATION 审中-公开

    公开(公告)号：US20240289922A1

    公开(公告)日：2024-08-29

    申请号：US18430431

    申请日：2024-02-01

    Applicant: Apple Inc.

    Inventor： Jim C. Chou ,  Yun Gong

    IPC: G06T5/00 ,  G06T3/4046 ,  G06T3/4053 ,  G06T5/50 ,  G06T7/11

    CPC classification number: G06T5/00 ,  G06T3/4046 ,  G06T3/4053 ,  G06T5/50 ,  G06T7/11 ,  G06T2207/20084 ,  G06T2207/20192 ,  G06T2207/20221

    Abstract: Methods and systems include neural network-based image processing and blending circuitry to blend an output of the neural network to compensate for potential artifacts from the neural network-based image processing. The neural network(s) apply image processing to image data using one or more neural networks as processed data. Enhance circuitry enhances the image data in a scaling circuitry to generate enhanced data. Blending circuitry receives the processed image data and the enhanced data along with an image plane of the processed data. The blending circuitry also determines whether the image processing using the one or more neural networks has applied a change to the image data greater than a threshold amount. The blending circuitry then, based at least in part in response to the change being greater than the threshold amount and/or edge information of the image data, blends the processed data with the enhanced data.

    IMAGE BLENDING MODES SYSTEMS AND METHODS
    39.
    发明公开
    IMAGE BLENDING MODES SYSTEMS AND METHODS 审中-公开

    公开(公告)号：US20240096010A1

    公开(公告)日：2024-03-21

    申请号：US17934138

    申请日：2022-09-21

    Applicant: Apple Inc.

    Inventor： Yun Gong ,  Jim C. Chou ,  Guy Cote

    IPC: G06T15/50

    CPC classification number: G06T15/503 ,  G06T3/0093

    Abstract: A device may include an electronic display to display an image frame based on blended image data and image processing circuitry to generate the blended image data by combining first image data and second image data via a blend operation. The blend operation may include receiving graphics alpha data indicative of a transparency factor to be applied to the first image data to generate a first layer of the blend operation. The blend operation may also include overlaying the first layer onto a second layer that is based on the second image data. Overlaying the first layer onto the second layer may include adding first pixels values of the first image data that include negative pixel values and are augmented by the transparency factor to second pixel values of the second image data to generate blended pixel values of the blended image data.

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